2

ClockWorks™

SY89825U

Micrel

LOGIC SYMBOL

CLK_SEL

LVDS_CLK

/LVDS_CLK

LVPECL_CLK

/LVPECL_CLK

OE

0

1

22

22

Q0 - Q21

/Q0 - /Q21

LEN

D

Q

Pin

Function

LVDS_CLK,

Differential LVDS Inputs

/LVDS_CLK

(Internal 100

Ω termination included)

LVPECL_CLK,

Differential LVPECL Inputs.

/LVPECL_CLK

CLK_SEL

Input CLK Select (LVTTL)

OE

Output Enable (LVTTL)

Differential LVPECL Outputs.

Terminate with 50

Ω to V

GND

Ground

Power Supply. Connect to

internally connected

Power Supply for Output Buffer.

PIN NAMES

CLK_SEL

0

0

LOW

HIGH

0

1

LOW

HIGH

1

0

LVDS_CLK

/LVDS_CLK

1

1

LVPECL_CLK

/LVPECL_CLK

TRUTH TABLE

NOTE:

1. The OE (output enable) signal is synchronized with the low level of the

LVDS_CLK and LVPECL_CLK signal.

Signal

I/O

Level

LVDS_CLK, /LVDS_CLK

Input

LVDS

Output

LVPECL

LVPECL_CLK, /LVPECL_CLK

Input

LVPECL

CLK_SEL, OE

Input

LVCMOS/LVTTL

SIGNAL GROUPS

NOTE:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions

for extended periods may affect device reliability.

Symbol

Rating

Value

Unit

–0.5 to +4.0

V

Input Voltage

V

DC Output Current

–50

mA

Tstore

Storage Temperature

–65 to +150

°C

θ

JA

Package Thermal Resistance (Junction-to-Ambient)

With exposed pad soldered to GND

– Still-Air (multi-layer PCB)

23

°C/W

– 200lfpm (multi-layer PCB)

18

°C/W

– 500lfpm (multi-layer PCB)

15

°C/W

Exposed pad

not soldered to GND

– Still-Air (multi-layer PCB)

44

°C/W

– 200lfpm (multi-layer PCB)

36

°C/W

– 500lfpm (multi-layer PCB)

30

°C/W

θ

JC

Package Thermal Resistance

4.3

°C/W

(Junction-to-Case)