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TPS72615 Datasheet(PDF) 2 Page - Texas Instruments

Part # TPS72615
Description  LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR
PDF  16 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS72615 Datasheet(HTML) 2 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403F – MAY 2002 – REVISED MAY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
VOUT
TPS726xxxyyyz
XXX is nominal output voltage (for example, 126 = 1.26V, 15 = 1.5V).
YYY is package designator.
Z is package quantity.
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage, VI(2)
–0.3 to 7
V
Voltage range at EN, FB
–0.3 to VI + 0.3
V
Voltage on RESET
VIN + 0.3
V
Voltage on OUT
6
V
ESD rating, HBM
2
kV
Continuous total power dissipation
See Dissipation Rating Table
Operating junction temperature range, TJ
–50 to 150
°C
Maximum junction temperature range, TJ
150
°C
Storage temperature, Tstg
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
PACKAGE
BOARD
RθJC
RθJA
DDPAK
High K(1)
2 °C/W
23 °C/W
SOT223
Low K(2)
15 °C/W
53 °C/W
(1)
The JEDEC high K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2)
The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.
2



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