M58BW032BT datasheet(18/60 Pages) STMICROELECTRONICS

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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB

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Burst Configuration Register

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform.

The Burst Configuration Register is set through

the Command Interface and will retain its informa-

tion until it is re-configured, the device is reset, or

the device goes into Reset/Power-Down mode.

The Burst Configuration Register bits are de-

scribed in Table 6. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation. Refer to Figure 5 for

examples of synchronous burst configurations.

Read Select Bit (M15). The

Read

Select

bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous accesses.

Standby Disable Bit (M14). The Standby Dis-

able Bit, M14, is used to disable the Standby

mode. When the Standby bit is ‘1’, the device will

not enter Standby mode when Chip Enable goes

High, VIH.

X-Latency Bits (M13-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table

6., Burst Configuration Register. The X-Latency

bits should also be selected in accordance with

Note: 1. below Table 6., Burst Configuration Reg-

ister.

Y-Latency Bit (M9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table

6., Burst Configuration Register and Note 2.for

valid combinations of the Y-Latency, the X-Laten-

cy and the Clock frequency.

Valid Data Ready Bit (M8). The

Valid

Data

Ready bit controls the timing of the Valid Data

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the rising clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

Wrap Burst Bit (M3). The burst reads can be

confined inside the 4 or 8 Word boundary (wrap) or

overcome the boundary (no wrap). The Wrap

Burst bit is used to select between wrap and no

wrap. When the Wrap Burst bit is set to ‘0’ the

burst read wraps; when it is set to ‘1’ the burst read

does not wrap.

Burst Length Bit (M2-M0). The Burst Length bits

set the maximum number of Double-Words that

can be output during a Synchronous Burst Read

operation before the address wraps. Burst lengths

of 4 or 8 and continuous burst are available.

Table 6., Burst Configuration Register gives the

valid combinations of the Burst Length bits that the

memory accepts; Table 7., Burst Type Definition,

gives the sequence of addresses output from a

given starting address for each length.

If either a Continuous or a No Wrap Burst Read

has been initiated the device will output data syn-

chronously. Depending on the starting address,

the device activates the Valid Data Ready output

to indicate that a delay is necessary before the

data is output. If the starting address is aligned to

a 4 Double Word boundary, the continuous burst

mode will run without activating the Valid Data

Ready output. If the starting address is not aligned

to a 4 Double Word boundary, Valid Data Ready is

activated to indicate that the device needs an in-

ternal delay to read the successive words in the ar-

ray.

M10, M7 to M4 are reserved for future use.

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