PI7C21P100 datasheet(13/77 Pages) PERICOM

13 / 77 page

PI7C21P100

2-PORT PCI-X BRIDGE

ADVANCE INFORMATION

Page 13 of 77

June 10, 2005 Revision 1.06

3.2.3

SECONDARY BUS INTERFACE SIGNALS

Name

Pin #

Type

Description

S_AD[31:0]

N22, N21, P22, P21,

M23, P20, N23, R22,

T23, R21, W23, T22,

U22, U21, V22, V21,

W21, V20, AA20,

AB18, Y18, AA16,

AB15, AC17, AA13,

AA12, AC15, AB11,

AC11, AC9, AB9,

AA9

Secondary Address/Data: Multiplexed address and data

bus. Address is indicated by S_FRAME# assertion.

Write data is stable and valid when S_IRDY# is asserted

and read data is stable and valid when S_IRDY# is

asserted. Data is transferred on rising clock edges when

both S_IRDY# and S_TRDY# are asserted. During bus

idle, PI7C21P100 drives S_AD[31:0] to a valid logic

level when the bridge is granted the bus.

S_CBE[3:0]#

AA15, AB14, AB16,

AB12

Secondary Command/Byte Enables: Multiplexed

command field and byte enable field. During address

phase, the initiator drives the transaction type on these

pins. The initiator then drives the byte enables during

data phases. During bus idle, PI7C21P100 drives

S_CBE[3:0] to a valid logic level when the bridge is

granted the bus.

S_PAR

AA17

Secondary Parity: S_PAR is an even parity of

S_AD[31:0] and S_CBE[3:0] (i.e. an even number of

1’s). S_PAR is valid and stable one cycle after the

address phase (indicated by assertion of S_FRAME#) for

address parity. For write data phases, S_PAR is valid

one clock after S_IRDY# is asserted. For read data

phase, S_PAR is valid one clock after S_TRDY# is

asserted. Signal S_PAR is tri-stated one cycle after the

S_AD lines are tri-stated. During bus idle, PI7C21P100

drives S_PAR to a valid logic level when the bridge is

granted the bus.

S_FRAME#

AA14

STS

Secondary FRAME (Active LOW): Driven by the

initiator of a transaction to indicate the beginning and

duration of an access. The de-assertion of S_FRAME#

indicates the final data phase requested by the initiator.

Before being tri-stated, it is driven HIGH for one cycle.

S_IRDY#

AC19

STS

Secondary IRDY (Active LOW): Driven by the

initiator of a transaction to indicate its ability to

complete current data phase on the secondary side. Once

asserted in a data phase, it is not de-asserted until the end

of the data phase. Before tri-stated, it is driven HIGH

for one cycle.

S_TRDY#

Y14

STS

Secondary TRDY (Active LOW): Driven by the target

of a transaction to indicate its ability to complete current

data phase on the secondary side. Once asserted in a

data phase, it is not de-asserted until the end of the data

phase. Before tri-stated, it is driven HIGH for one cycle.

S_DEVSEL#

AC21

STS

Secondary Device Select (Active LOW): Asserted by

the target indicating that the device is accepting the

transaction. As a master, PI7C21P100 waits for the

assertion of this signal within 5 cycles of S_FRAME#

assertion; otherwise, terminate with master abort. Before

tri-stated, it is driven HIGH for one cycle.

S_STOP#

AB20

STS

Secondary STOP (Active LOW): Asserted by the

target indicating that the target is requesting the initiator

to stop the current transaction. Before tri-stated, it is

driven HIGH for one cycle.

S_LOCK#

AC20

STS

Secondary LOCK (Active LOW): Asserted by an

initiator, one clock cycle after the first address phase of a

transaction, when it is propagating a locked transaction

downstream. PI7C21P100 does not propagate locked

transactions upstream.

S_PERR#

AB17

STS

Secondary Parity Error (Active LOW): Asserted

when a data parity error is detected for data received on

the secondary interface. Before being tri-stated, it is

driven HIGH for one cycle.

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