© 2002 Fairchild Semiconductor Corporation

DS500502

www.fairchildsemi.com

March 2001

Revised April 2002

FIN1018

3.3V LVDS 1-Bit High Speed Differential Receiver

General Description

This single receiver is designed for high speed intercon-

nects utilizing Low Voltage Differential Signaling (LVDS)

technology. The receiver translates LVDS levels, with a typ-

ical differential input threshold of 100 mV, to LVTTL signal

levels. LVDS provides low EMI at ultra low power dissipa-

tion even at high frequencies. This device is ideal for high

speed transfer of clock or data.

The FIN1018 can be paired with its companion driver, the

FIN1017, or with any other LVDS driver.

Features

■ Greater than 400Mbs data rate

■ 3.3V power supply operation

■ 0.4ns maximum pulse skew

■ 2.5ns maximum propagation delay

■ Low power dissipation

■ Power-Off protection

■ Fail safe protection for open-circuit, shorted and termi-

nated conditions

■ Meets or exceeds the TIA/EIA-644 LVDS standard

■ Flow-through pinout simplifies PCB layout

■ 8-Lead SOIC and US-8 packages save space

Ordering Code:

Pin Descriptions

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

Fail Safe

= Open, Shorted, Terminated

Connection Diagrams

8-Lead SOIC

Pin Assignment for US-8 Package

TOP VIEW

Order Number

Package Number

Package Description

FIN1018M

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TUBE]

FIN1018MX

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TAPE and REEL]

FIN1018K8X

MAB08A

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

[TAPE and REEL]

Pin Name

Description

LVTTL Data Output

Non-inverting Driver Input

Inverting Driver Input

Power Supply

GND

Ground

NC

No Connect

Input

Outputs

LH

L

HL

H

Fail Safe Condition

H