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ADV7612 Datasheet(PDF) 13 Page - Analog Devices

Part # ADV7612
Description  Dual Port, Xpressview, 225 MHz HDMI Receiver
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7612 Datasheet(HTML) 13 Page - Analog Devices

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Data Sheet
ADV7612
Rev. E | Page 13 of 20
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7612 is highly flexible. The pixel
output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4
RGB. The pixel data supports both single and double data rates
modes1. In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit
4:4:4 output is possible. In DDR mode, the pixel output port can
be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB.
Bus rotation is supported. Table 5 to Table 8 outline the different
output formats that are supported. All output modes are controlled
via I2C.
1 DDR mode is only supported only up to 50 MHz (an equivalent to data rate
clocked 100 MHz clock in SDR mode).
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include the following:
8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded
time codes and/or HS, VS, and FIELD output signals
16-/20-/24-bit YCrCb with embedded time codes and/or
HS and VS/FIELD pin timing
24-/30-/36-bit YCrCb/RGB with embedded time codes
and/or HS and VS/FIELD pin timing
DDR 8-/10-/12-bit 4:2:2 YCrCb
DDR 12-/24-/30-/36 bit 4:4:4 RGB
Table 5. SDR 4:2:2 Output Modes
SDR 4:2:2
OP_FORMAT_SEL[7:0]
0x01
0x1
0x2
0x6
0x0A
Pixel Output
8-Bit SDR
ITU-R BT.656
Mode 0
10-Bit SDR
ITU-R BT.656
Mode 0
12-Bit SDR
ITU-R BT.656
Mode 0
12-Bit SDR
ITU-R BT.656
Mode 1
12-Bit SDR
ITU-R BT.656
Mode 2
P35
High-Z
High-Z
High-Z
High-Z
Y3, Cb3, Cr3
P34
High-Z
High-Z
High-Z
High-Z
Y2, Cb2, Cr2
P33
High-Z
High-Z
High-Z
High-Z
Y1, Cb1, Cr1
P32
High-Z
High-Z
High-Z
High-Z
Y0, Cb0, Cr0
P31
High-Z
High-Z
High-Z
High-Z
High-Z
P30
High-Z
High-Z
High-Z
High-Z
High-Z
P29
High-Z
High-Z
High-Z
Y1, Cb1, Cr1
High-Z
P28
High-Z
High-Z
High-Z
Y0, Cb0, Cr0
High-Z
P27
High-Z
High-Z
High-Z
High-Z
High-Z
P26
High-Z
High-Z
High-Z
High-Z
High-Z
P25
High-Z
High-Z
High-Z
High-Z
High-Z
P24
High-Z
High-Z
High-Z
High-Z
High-Z
P23
Y7, Cb7, Cr7
Y9, Cb9, Cr9
Y11, Cb11, Cr11
Y11, Cb11, Cr11
Y11, Cb11, Cr11
P22
Y6, Cb6, Cr6
Y8, Cb8, Cr8
Y10, Cb10, Cr10
Y10, Cb10, Cr10
Y10, Cb10, Cr10
P21
Y5, Cb5, Cr5
Y7, Cb7, Cr7
Y9, Cb9, Cr9
Y9, Cb9, Cr9
Y9, Cb9, Cr9
P20
Y4, Cb4, Cr4
Y6, Cb6, Cr6
Y8, Cb8, Cr8
Y8, Cb8, Cr8
Y8, Cb8, Cr8
P19
Y3, Cb3, Cr3
Y5, Cb5, Cr5
Y7, Cb7, Cr7
Y7, Cb7, Cr7
Y7, Cb7, Cr7
P18
Y2, Cb2, Cr2
Y4, Cb4, Cr4
Y6, Cb6, Cr6
Y6, Cb6, Cr6
Y6, Cb6, Cr6
P17
Y1, Cb1, Cr1
Y3, Cb3, Cr3
Y5, Cb5, Cr5
Y5, Cb5, Cr5
Y5, Cb5, Cr5
P16
Y0, Cb0, Cr0
Y2, Cb2, Cr2
Y4, Cb4, Cr4
Y4, Cb4, Cr4
Y4, Cb4, Cr4
P15
High-Z
Y1, Cb1, Cr1
Y3, Cb3, Cr3
Y3, Cb3, Cr3
High-Z
P14
High-Z
Y0, Cb0, Cr0
Y2, Cb2, Cr2
Y2, Cb2, Cr2
High-Z
P13
High-Z
High-Z
Y1, Cb1, Cr1
High-Z
High-Z
P12
High-Z
High-Z
Y0, Cb0, Cr0
High-Z
High-Z
P11
High-Z
High-Z
High-Z
High-Z
High-Z
P10
High-Z
High-Z
High-Z
High-Z
High-Z
P9
High-Z
High-Z
High-Z
High-Z
High-Z
P8
High-Z
High-Z
High-Z
High-Z
High-Z
P7
High-Z
High-Z
High-Z
High-Z
High-Z
P6
High-Z
High-Z
High-Z
High-Z
High-Z
P5
High-Z
High-Z
High-Z
High-Z
High-Z
P4
High-Z
High-Z
High-Z
High-Z
High-Z
P3
High-Z
High-Z
High-Z
High-Z
High-Z
P2
High-Z
High-Z
High-Z
High-Z
High-Z
P1
High-Z
High-Z
High-Z
High-Z
High-Z
P0
High-Z
High-Z
High-Z
High-Z
High-Z
1 Modes 0x00, 0x01, 0x02, 0x06 and 0x0A require additional writes to IO Map reg. 0x19[7:6]=2’b11 and IO Map reg.0x33[6]=1



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