ADV7613 datasheet(6/13 Pages) AD

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ADV7613

Data Sheet

Rev. B | Page 6 of 13

Parameter

Symbol

Min

Typ

Max

Unit

Start Condition Setup Time

600

SDA Setup Time

100

SCL and SDA Rise Time

300

SCL and SDA Fall Time

300

Stop Condition Setup Time

0.6

µs

RESET FEATURE

Reset Pulse Width

Reset Pulse to First I2C Transaction

I2S PORT, MASTER MODE

SCLK Mark to Space Ratio

t15:t16

45:55

55:45

% Duty Cycle

Left/Right Clock (LRCLK) Data Transition Time

t17

t18

I2Sx1 Data Transition Time

t19

t20

I2Sx signals (where x = 0, 1, 2, or 3) are available on the AP1 to AP4 pins (see Table 6).

Timing Diagrams

Figure 3. I2C Timing

Figure 4. I2S Timing

SDA

SCL

SCLK

LRCLK

I2Sx

LEFT JUSTIFIED

MODE

I2Sx

RIGHT JUSTIFIED

MODE

I2Sx

I2S MODE

MSB

MSB – 1

t15

t16

t17

t19

t20

t18

MSB

MSB – 1

LSB

MSB

t19

t20

t19

t20

NOTES

1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN.

2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE

ON THE FOLLOWING PINS:AP1, AP2, AP3, AND AP4.

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