WM8974 datasheet(60/89 Pages) CIRRUS

60 / 89 page

WM8974

Rev 4.7

Set BIASEN = 1, BUFIOEN = 1, BUFDCOPEN = 1 and also the VMIDSEL[1:0] bits in the

Power Management 1 register. * Notes 1 and 2.

Wait for the VMID supply to settle. * Note 2.

Enable DAC by setting DACEN = 1.

Enable mixers as required.

Enable output stages as required.

Power Down (all cases):

Soft mute DAC by setting DACMU = 1.

Disable power management register 1 by setting R1[8:0]=0x00.

Disable all other output stages.

Turn off external power supplies.

Notes:

This step enables the internal device bias buffer and the VMID buffer for unassigned

inputs/outputs. This will provide a start-up reference voltage for all inputs and outputs. This will

cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x

(AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2).

Choose the value of the VMIDSEL bits based on the start-up time (VMIDSEL=10 for slowest

start-up, VMIDSEL=11 for fastest start-up). Start-up time is defined by the value of the

VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID.

In addition to the power on sequence, it is recommended that the zero cross functions are used when

changing the volume in the PGAs to avoid any audible pops or clicks.

pora

DGND

Internal POR active

Device Ready

No Power

por_off

Power Supply

POR

I2S Clocks

ADC Internal

State

midrail_on

Analogue Inputs

ADCDAT pin

ADCEN bit

Power down

Init

Normal Operation

Init

Power down

ADC enabled

ADC off

adcint

DNC

INPPGAEN bit

adcint

INPPGA enabled

DNC

POR

POR Undefined

VMID enabled

VMIDSEL/

BIASEN bits

AVDD/2

midrail_off

(Note 1)

(Note 2)

(Note 3)

(Note 4)

por_on

Figure 34 ADC Power Up and Down Sequence (not to scale)

WM8974 Datasheet(PDF) 60 Page - Cirrus Logic

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