Low Skew, 1-to-16

Differential-to-LVDS Clock Distribution Chip

ICS8516

DATASHEET

8516 REVISION B 6/11/15

1

©2015 Integrated Device Technology, Inc.

The ICS8516 is a low skew, high performance 1-to-16 Differential-

to-LVDS Clock Distribution Chip.The ICS8516 CLK, nCLK pair can

accept any differential input levels and translates them to 3.3V LVDS

output levels. Utilizing Low Voltage Differential Signaling (LVDS),

the ICS8516 provides a low power, low noise, point-to-point

solution for distributing clock signals over controlled impedances

of 100

Ω.

Dual output enable inputs allow the ICS8516 to be used in a

1-to-16 or 1-to-8 input/output mode.

Guaranteed output and part-to-part skew specifications make

the ICS8516 ideal for those applications demanding well

defined performance and repeatability.

• Sixteen differential LVDS outputs

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 700MHz

• Translates any differential input signal (LVPECL, LVHSTL,

SSTL, DCM) to LVDS levels without external bias networks

• Translates any single-ended input signal to LVDS

with resistor bias on nCLK input

• Multiple output enable inputs for disabling unused

outputs in reduced fanout applications

• LVDS compatible

• Output skew: 90ps (maximum)

• Part-to-part skew: 500ps (maximum)

• Propagation delay: 2.4ns (maximum)

• Additive phase jitter, RMS: 148fs (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead-free RoHS compliant package

48-Lead LQFP

7mm x 7mm x 1.4mm body package

Y Package

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