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LP5030RJVR Datasheet(PDF) 48 Page - Texas Instruments |
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LP5030RJVR Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 57 page ![]() Graph Placeholder C00 Graph Placeholder C00 RIREF= KIREF × VIREF I(MAX_SET) =105 ×0.7÷0.015=4900 Ÿ 48 LP5030, LP5036 SLVSEH1 – SEPTEMBER 2018 www.ti.com Product Folder Links: LP5030 LP5036 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Typical Application (continued) The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used, depending on the bus capacitance, I/O voltage, and the desired communication speed. Selecting a smaller value increases the pullup speed, but slows the pulldown speed. If they want pull up quickly select the samller one but it will impact the pull down speed. VCAP is the internal LDO output pin. This pin must be connected through a 1-μF capacitor to GND. Put the capacitor as close to the device as possible. TI recommends having a 1-μF capacitor between VCC and GND to ensure proper operation. Put the capacitor as close to the device as possible. 9.2.3 Application Curves Figure 74. Figure 75. |
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