AD9574BCPZ datasheet(14/35 Pages) AD

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AD9574

Data Sheet

Rev. B | Page 14 of 35

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9574

TOP VIEW

(Not to Scale)

REF0_P

VDD_REF0

REF0_N

VDD_REF1

REF1_P

REF1_N

PPR2

VDD_OUT01

OUT0_N

OUT0_P

OUT1_P

OUT1_N

REFMON

PPR4

PPR3

OUT4_P

OUT4_N

VDD_OUT4

VDD_OUT5

OUT5_N

OUT5_P

REF_FLO

REF_FHI

VDD_OUT23

NOTES

1. THE EXPOSED DIE PAD MUST BE CONNECTED

TO THE POWER SUPPLY COMMON (GND).

Figure 4. Pin Configuration

Table 18. Pin Function Descriptions

Pin No.

Mnemonic

Input/Output

Pin Type

Description

REF0_P

Input

Configurable

clock input

Reference Clock Input 0, Positive. Configurable via PPR0 (Pin 47).

REF0_N

Input

Configurable

clock input

Reference Clock Input 0, Negative. Configurable via PPR0 (Pin 47).

VDD_REF0

Input

Power

3.3 V Input Supply for Reference Clock Input 0 (REF0_x). This pin supplies the

single-ended input receiver and internal low dropout (LDO) regulator for the

differential receiver.

VDD_REF1

Input

Power

3.3 V Input Supply for Reference Clock Input 1 (REF1_x). This pin supplies the

single-ended input receiver and internal LDO regulator for the differential

receiver.

REF1_N

Input

Configurable

clock input

Reference Clock Input 1, Negative. Configurable via PPR0 (Pin 47).

REF1_P

Input

Configurable

clock input

Reference Clock Input 1, Positive. Configurable via PPR0 (Pin 47).

PPR2

Input

Control

Pin Program Reader 2. Connect a resistor to this pin to configure the OUT0 and

OUT1 channels (see the PPR2—OUT0 and OUT1 Configuration section for more

information).

VDD_OUT01

Input

Power

3.3 V Supply. 3.3 V input for the CMOS drivers of OUT0_x and OUT1_x and the

source for an internal 1.8 V LDO regulator for the differential drivers of OUT0_x

and OUT1_x.

OUT0_N

Output

Configurable

clock output

Clock Output 0, Negative. Configurable via PPR2 (Pin 7).

OUT0_P

Output

Configurable

clock output

Clock Output 0, Positive. Configurable via PPR2 (Pin 7).

OUT1_P

Output

Configurable

clock output

Clock Output 1, Positive. Configurable via PPR2 (Pin 7).

OUT1_N

Output

Configurable

clock output

Clock Output 1, Negative. Configurable via PPR2 (Pin 7).

VDD_PLL

Input

Power

3.3 V Input to the Internal LDO Regulator for the PLL.

Output

3.3 V CMOS

PLL Lock Detector Status. Logic 0 = unlocked; Logic 1 = locked.

Input/Output

Analog

Loop Filter. Connect a capacitor or series RC network (see Table 32) from this pin

to LDO_BYP (Pin 16).

LDO_BYP

Output

Analog

LDO Bypass. Connect a 470 nF capacitor from this pin to GND.

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