AD7790 datasheet(13/20 Pages) AD

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AD7790

Rev. 0 | Page 13 of 20

ADC CIRCUIT INFORMATION

OVERVIEW

The AD7790 is a low power ADC that incorporates a ∑-∆

modulator, a buffer, a PGA, and on-chip digital filtering intend-

ed for the measurement of wide dynamic range, low frequency

signals such as those in pressure transducers, weigh scales, and

temperature measurement applications.

The part has one differential input that can be buffered or

unbuffered. Buffering the input channel means that the part can

accommodate significant source impedances on the analog

input and that R, C filtering (for noise rejection or RFI reduc-

tion) can be placed on the analog input, if required. The device

requires an external reference of 2.5 nominal. Figure 7 shows

the basic connections required to operate the part.

03538-0-006

IN+

µF

0.1

µF

IN–

OUT–

POWER

SUPPLY

OUT+

REFIN(+)

DOUT/RDY

SCLK

VDD

GND

AIN(+)

AIN(–)

REFIN(–)

AD7790

MICROCONTROLLER

Figure 7. Basic Connection Diagram

The output rate of the AD7790 (fADC) is user programmable

with the settling time equal to 2 × tADC. Normal mode rejection

is the major function of the digital filter. Table 13 lists the avail-

able output rates from the AD7790. Simultaneous 50 Hz and

60 Hz rejection is optimized when the update rate equals

16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this

update rate (see Figure 6).

NOISE PERFORMANCE

Table 14 shows the output rms noise, rms resolution, and peak-

to-peak resolution (rounded to the nearest 0.5 LSB) for the

different update rates and input ranges for the AD7790. The

numbers given are with a reference of 2.5 V. The numbers are

typical and generated with a differential input voltage of 0 V.

The peak-to-peak resolution figures represent the resolution for

which there will be no code flicker within a six-sigma limit. The

output noise comes from two sources. The first is the electrical

noise in the semiconductor devices (device noise) used in the

implementation of the modulator. The second is quantization

noise, which is added when the analog input is converted into

the digital domain. The device noise is at a low level and is

independent of frequency. The quantization noise starts at an

even lower level but rises rapidly with increasing frequency to

become the dominant noise source.

Table 14. Typical Peak-to-Peak Resolution (Effective

Resolution) vs. Update Rate and Input Range

Input Range

Update Rate

±0.3125

±0.625

±1.25

±2.5

9.5

16 (16)

13.3

16 (16)

16.7

16 (16)

16.6

16 (16)

15.5 (16)

16 (16)

33.3

14.5 (16)

15.5 (16)

16 (16)

100

11.5 (14)

12.5 (15)

13.5 (16)

14.5 (16)

120

11 (13.5)

12 (14.5)

13 (15.5)

14 (16)

REDUCED CURRENT MODES

The AD7790 has a current consumption of 160 µA maximum

when operated with the buffer enabled and with a 5 V power

supply. The power can be reduced further by setting bits CDIV1

and CDIV0 in the filter register appropriately (see Table 15).

By setting these bits, the internal clock is divided by 2, 4, or 8

before being applied to the modulator and filter, resulting in a

reduction in the digital current.

When the internal clock is reduced, the update rate will also be

reduced. For example, if the filter bits are set to give an update

rate of 16.6 Hz when the AD7790 is operated in full clock mode,

the update rate will equal 8.3 Hz in divide by 2 mode. In these

low power modes, there may be some degradation in the ADC

performance.

Table 15. Low Power Mode Selection

CDIV[1:0]

Clock

Typ Current, Buffered (µA)

Typ Current, Unbuffered (µA)

50 Hz/60 Hz Rejection (dB)

146

1/2

1/4

1/8

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