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MLX80002 Datasheet(PDF) 23 Page - Melexis Microelectronic Systems |
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MLX80002 Datasheet(HTML) 23 Page - Melexis Microelectronic Systems |
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23 / 38 page ![]() MLX80002/MLX80004 Enhanced Universal Dual/Quad LIN Transceiver Datasheet Revision 021 – Sept 2016 Page 23 of 38 9.8. TxDx faulty start protection After power-on or wake-up a dominant level on TxDx will not lead to a dominant LINx level if the IC is being switched into an active mode. Only in case of recessive level before applying the first dominant level the transmit path will be enabled. 9.9. RxDx dominant time-out A dominant LINx level longer than the specified time (typ. 40ms) indicates a faulty blocked bus. The master pull-up resistor of the affected LIN channel will be disconnected from the network in order to prevent thermal overload conditions or failure currents from the battery without any intervention from the microcontroller. Only a weak pull-up current (typ.60uA) is applied on the LIN bus. The RxD time-out will be reset with the next dominant -> recessive transition on the LIN bus if the failure disappears. The RxDx time-out is only active in the Enhanced Master Mode, while the master termination is enabled. 9.10. TxDx dominant time-out In case of a faulty blocked permanent dominant level on pin TxDx the transmit path will be disabled after the specified time tTxDx_to (typ. 40ms). The data transmission is released again as soon as the failure disappears by the next rising edge of TxDx. The TxDx time-out is active in both, the Standard Transceiver and Enhanced Master Mode. |
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