7

LT4250L/LT4250H

4250lhf

Hot Circuit Insertion

When circuit boards are inserted into a live – 48V backplane,

the bypass capacitors at the input of the board’s power

module or switching power supply can draw huge tran-

sient currents as they charge up. The transient currents

can cause permanent damage to the board’s components

and cause glitches on the system power supply.

The LT4250 is designed to turn on a board’s supply

voltage in a controlled manner, allowing the board to be

safely inserted or removed from a live backplane. The chip

also provides undervoltage, overvoltage and overcurrent

protection while keeping the power module off until its

input voltage is stable and within tolerance.

Power Supply Ramping

The input to the power module on a board is controlled by

placing an external N-channel pass transistor (Q1) in the

power path (Figure 6a, all waveforms are with respect to

detection and R2 prevents high frequency oscillations.

Resistors R4, R5 and R6 provide undervoltage and over-

voltage sensing. By ramping the gate of Q1 up at a slow

rate, the inrush current charging load capacitors C3 and

C4 can be limited to a safe value when the board makes

connection.

Resistor R3 and capacitor C2 act as a feedback network to

accurately control the inrush current. The C2 capacitor can

be calculated with the following equation:

C2 = (45

input capacitance.

Capacitor C1 and resistor R3 prevent Q1 from momen-

tarily turning on when the power pins first make contact.

Without C1 and R3, capacitor C2 would pull the gate of Q1

LT4250 could power up and actively pull the gate low. By

placing capacitor C1 in parallel with the gate capacitance

of Q1 and isolating them from C2 using resistor R3 the

problem is solved. The value of C1 is given by:

C

VV

V

CC

INMAX

TH

TH

GD

12

=

−









•+

()

C1

R3 should not exceed a value that produces an

R3 • C2 time-constant of 150

µs. A 1k value for R3 will

ensure this for C2 values up to 150nF.

The waveforms are shown in Figure 6b. When the power

pins make contact, they bounce several times. While the

contacts are bouncing, the LT4250 senses an undervoltage

condition and the GATE is immediately pulled low when

the power pins are disconnected.

Once the power pins stop bouncing, the GATE pin starts to

ramp up. When Q1 turns on, the GATE voltage is held

constant by the feedback network of R3 and C2. When the

DRAIN voltage has finished ramping, the GATE pin then

ramps to its final value.

Figure 6a. Inrush Control Circuitry

+

LT4250H

PWRGD

UV = 38.5V

OV = 71V

SENSE

C1

470nF

25V

C3

0.1

µF

100V

C4

100

µF

100V

C5

100

µF

16V

Q1

IRF530

R2

10

Ω

5%

R3

1k, 5%

C2

15nF

100V

R4

549k

1%

R5

6.49k

1%

R6

10k

1%

R1

0.02

Ω

5%

4

3

2

OV

–48V RTN

–48V RTN

(SHORT PIN)

– 48V

UV

56

8

7

1

GATE

DRAIN

VICOR

VI-J30-CY

+

–

+

5V

4250 F06a

GATE IN

–

+

*

* DIODES INC. SMAT70A

4

3

2

1

Figure 6b. Inrush Control Waveforms

INRUSH

CURRENT

500mA/DIV

10V/DIV

DRAIN

50V/DIV

50V/DIV

25ms/DIV

4250 F06b

CONTACT

BOUNCE

MODULE

TURN-ON

MODULE

TURN-ON

CONTACT

BOUNCE