ADF4350BCPZ datasheet(12/34 Pages) AD

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ADF4350

Data Sheet

Rev. B | Page 12 of 34

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4350 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details,

see Figure 26). Figure 19 shows the MUXOUT section in

block diagram form.

DGND

DVDD

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

RESERVED

THREE-STATE OUTPUT

DVDD

Figure 19. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4350 digital section includes a 10–bit RF R counter,

a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit

modulus counter. Data is clocked into the 32–bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined by

the state of the three control bits (C3, C2, and C1) in the shift

Figure 2. The truth table for these bits is shown in Table 5.

Figure 23 shows a summary of how the latches are programmed.

Table 5. C3, C2, and C1 Truth Table

Control Bits

PROGRAM MODES

Table 5 and Figure 23 through Figure 29 show how the program

modes are to be set up in the ADF4350.

A number of settings in the ADF4350 are double buffered.

These include the modulus value, phase value, R counter value,

reference doubler, reference divide-by-2, and current setting.

This means that two events have to occur before the device uses

a new value of any of the double buffered settings. First, the

new value is latched into the device by writing to the appropriate

For example, any time the modulus value is updated, Register 0

(R0) must be written to, to ensure the modulus value is loaded

correctly. Divider select in Register 4 (R4) is also double buf-

fered, but only if DB13 of Register 2 (R2) is high.

VCO

The VCO core in the ADF4350 consists of three separate VCOs

each of which uses 16 overlapping bands, as shown in Figure 20,

to allow a wide frequency range to be covered without a large

VCO sensitivity (KV) and resultant poor phase noise and spu-

rious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic at power-up or whenever Register 0

(R0) is updated.

VCO and band selection take 10 PFD cycles × band select clock

divider value. The VCO VTUNE is disconnected from the output

of the loop filter and is connected to an internal reference voltage.

2.8

2.4

2.0

1.6

0.8

1.2

0.4

FREQUENCY (MHz)

Figure 20. VTUNE vs. Frequency

The use the R counter output as the clock for the band select

logic. A programmable divider is provided at the R counter

output to allow division by 1 to 255 and is controlled by

Bits [BS8:BS1] in Register 4 (R4). When the required PFD

frequency is higher than 125 kHz, the divide ratio must be

set to allow enough time for correct band selection.

After band select, normal PLL action resumes. The nominal

value of KV is 33 MHz/V when the N-divider is driven from the

VCO output or this value divided by D. D is the output divider

value if the N-divider is driven from the RF divider output

(chosen by programming Bits [D12:D10] in Register 4 (R4).

The ADF4350 contains linearization circuitry to minimize

any variation of the product of ICP and KV to keep the loop

bandwidth constant.

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