AP3783R datasheet(12/17 Pages) DIODES

12 / 17 page

AP3783R

Document number: DS37448 Rev. 6 - 2

12 of 17

www.diodes.com

March 2016

AP3783R

Operation Principle Description (Cont.)

Gate Voltage

Drive Current

10V

6.5V

High Drive Durrent=110mA

Low Drive Current=43mA

11V

Miller Platform

Figure 5. Drive Current and Gate Voltage

Leading Edge Blanking (LEB) Time

When the power switch is turned on, a turn-on spike will occur on the sense-resistor. To avoid false turn off switch, a leading-edge blanking is

built in. During this blanking time, the current sense comparator is disabled and the external power switch cannot be turned off.

Adjustable Line Compensation and Fixed Cable Compensation

The AP3783R power system can adjust line compensation by changing the upper resistor at FB pin. The line compensation capability is

increased by decreasing the resistance of the upper FB resistor.

Cable compensation is fixed in AP3783R.

Valley Turn-on

When the off time (tOFF) is lower than 16ms, AP3783R power system can work with valley turn-on. It can reduce MOSFET switching on power

losses which is resulted from the equivalent output capacitance. At the same time, because of valley turn-on the switching frequency has the

random jitter feature, which will be benefit for conductive EMI performance. And valley turn-on can also reduce the power switch turn on spike

current and then result in the better radiative EMI performance.

Frequency Jitter

Even though the valley turn-on function can lead the random frequency jitter feature, an active frequency jitter function is added to AP3783R to

ensure the frequency jitter performance in the whole loading condition. By adjusting the VCS_REF with deviation of 5.0% every 256μs cycle, the

active frequency jitter can be realized.

Short Circuit Protection (SCP)

Short Circuit Protection (SCP) detection principle is similar to the normal output voltage feedback detection by sensing FB pin voltage. When

the detected FB pin voltage is below VFB(SCP) for a duration of about 128ms, the SCP is triggered. Then the AP3783R enters hiccup mode that

the IC immediately shuts down and then restarts, so that the VCC voltage changes between VTH_ST and UVLO threshold until VFB(SCP) condition

is removed.

As to the normal system startup, the time duration of FB pin voltage below VFB(SCP) should be less than tSCP to avoid entering SCP mode. But

for the output short condition or the output voltage below a certain level, the SCP mode will be triggered.

AP3783R Datasheet(PDF) 12 Page - Diodes Incorporated