Functional Block Description

The internal CPU, based on Harvard architechture, is a very compact 32-bit RISC engine.

Most instructions are executed in a single clock cycle under control of a 5-stage pipeline.

It also includes a 16 x 16-bit hardware multiplier with 32-bit result and saturation logic. A

32-bit barrel shifter and bit manipulation instructions accelerate complex bit operations.

The BCU initiates the bus cycles based on the physical addresses generated by the CPU.

When an instruction stored in external memory is executed and no bus cycle initiation is

requested by the CPU, the BCU creates a prefetch address to prefetch an instruction code

which is then inserted in the internal instruction queue.

The internal RAM, with a capacity of 4 or 8 Kbytes, is mapped from address FFFFE000H.

The CPU can access any data in one clock cycle.

The internal ROM (96 or 128 Kbytes) or Flash ROM (128 or 256 Kbytes) is mapped from

00000000H. The CPU can access any instruction from the ROM/Flash ROM in one clock cycle.

The Flash memory can be written and erased electrically.

The V853 has 67 input/output port pins that can be used alternatively as control pins.

The interrupt controller handles the interrupt request issued by internal peripheral

hardware and external sources. Up to 8 interrupt priority levels can be specified for each

interrupt request.

The clock generator produces the CPU operating clock. The internal frequency can be

selected as 5x or 1x of crystal frequency by using the internal PLL or 1/2x crystal frequency

without PLL. An external clock can be used instead of the clock generator. A clock-out

signal is available.

The RPU includes a 5-channel 16-bit timer/counter unit.

The serial interface includes two channels of CSI (Clocked Serial Interface) and two channels

which can be operated in the UART (Asynchronous Serial Interface) or the CSI mode. The

UART transfers data via the TxD and RxD pins. The baud rate is determined by the on-chip

dedicated baud rate generator. The CSI transfers data via the SO, SI and SCK pins at a baud

rate determined by the on-chip dedicated baud rate generator or an external clock.

An 8-channel A/D converter with 10-bit resolution and a 2-channel 8-bit D/A converter are

integrated.

A 2-channel PWM unit with different operating modes is available on chip.

CPU

Bus Control Unit

(BCU)

RAM

Serial Interface

Clock Generator

Real-time Pulse

Unit (RPU)/Timers

PROM Programming

Ports

Interrupt Controller

ROM

A/D Converter

PWM