AD9136BCPAZ datasheet(64/117 Pages) AD

64 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 64 of 117

When considering the trace width vs. copper weight and

thickness, the speed of the interface must be considered. At

multigigabit speeds, the skin effect of the conducting material

confines the current flow to the surface. Maximize the surface

area of the conductor by making the trace width made wider to

reduce the losses. Additionally, loosely couple differential traces

to accommodate the wider trace widths. This helps reduce the

crosstalk and minimize the impedance mismatch when the

traces must separate to accommodate components, vias,

connectors, or other routing obstacles. Tightly coupled vs.

loosely coupled differential traces are shown in Figure 71.

Figure 71. Tightly Coupled vs. Loosely Coupled Differential Traces

AC Coupling Capacitors

The AD9135/AD9136 require that the JESD204B input signals

be ac-coupled to the source. These capacitors must be 100 nF

and placed as close as possible to the transmitting logic device.

To minimize the impedance mismatch at the pads, select the

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

SYNCOUTx±, SYSREF±, and CLK± Signals

The SYNCOUTx± and SYSREF± signals on the AD9135/

AD9136 are low speed LVDS differential signals. Use controlled

impedance traces routed with 100 Ω differential impedance and

50 Ω to ground when routing these signals. As with the

SERDIN0± to SERDIN7± data pairs, it is important to keep

these signals separated from potential noise sources such as

high speed digital signals and noisy supplies.

Separate the SYNCOUTx± signal from other noisy signals,

because noise on the SYNCOUTx± may be interpreted as a

request for K characters. The SYNCOUTx± signal has two

modes of operation available for use. Register 0x2A5[0] defaults

to 0, which sets the SYNCOUTx± swing to normal swing mode.

When this bit is set to 1, the SYNCOUTx± swing is configured

for high swing mode. For more details, see Table 8.

It is important to keep similar trace lengths for the CLK± and

SYSREF± signals from the clock source to each of the devices

on either end of the JESD204B links (see Figure 72). If using a

clock chip that can tightly control the phase of CLK± and

SYSREF±, the trace length matching requirements are greatly

reduced.

Figure 72. SYSREF Signal and Device Clock Trace Length

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELY COUPLED

DIFFERENTIAL Tx LINES

CLOCK SOURCE

(AD9516-1, ADCLK925)

LANE 0

LANE 1

LANE N – 1

LANE N

DEVICE CLOCK

SYSREF

SYSREF TRACE LENGTH

DEVICE CLOCK TRACE LENGTH

DEVICE

AD9136BCPAZ Datasheet(PDF) 64 Page - Analog Devices

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