ICS952801 datasheet(9/22 Pages) ICST

9 / 22 page

Integrated

Circuit

Systems, Inc.

ICS952801

Advance Information

0719—01/22/03

2C Table: Function Control Register

Control

Function

Bit 7

PDEN

PD# Enable

Disable

Enable

Bit 6

PCICLK7

Output Control

Disable

Enable

Bit 5

WDS_EN

WD Soft Enable

Disable

Enable

Bit 4

PCICLK6

Output Control

Disable

Enable

Bit 3

AFS1

Async Rom SEL_1

Bit 2

AFS0

Async Rom SEL_0

Bit 1

AEN1

Bit 0

AEN0

Zclk/Agp/Pci Freq

Source Select Control

See Table 3: Async Z-CLK

Frequency Selection Table

See Table 4 : ZCLK, AGP &

PCI Frequency Source

Decode Table

1PWD

Name

Pin #

Byte 0

Type

Table 3: Asynchronous ZCLK Frequency Selection Table

Table 4: ZCLK, AGP & PCI Frequency Source Decode Table

Byte0 Bit3

Byte0 Bit2

ZCLK Frequency

Byte0 Bit1

Byte0 Bit0

ZCLK & AGP & PCI

64.01

See Table 1, QuadRom

Frequency Table

72.01

N-Programming for

AGP/PCI/ZCLK

82.30

See Table 1 for AGP/PCI,

Table 3 for ZCLK

144.02

N-Programming for AGP/PCI,

Table 3 for ZCLK

2C Table: Async N-Programming Frequency Select Register

Control

Function

Bit 7

N PLL3 Div7

Bit 6

N PLL3 Div6

Bit 5

N PLL3 Div5

Bit 4

N PLL3 Div4

Bit 3

N PLL3 Div3

Bit 2

N PLL3 Div2

Bit 1

N PLL3 Div1

Bit 0

N PLL3 Div0

2C Table: Reserved Register

Control

Function

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

The decimal

representation of N

PLL2 Div (7:0) + 8 is

equal to VCO divider

value for PLL2. Default

at power up =

66.67MHz

Name

1PWD

Type

PWD

Name

Type

Byte 2

Pin #

Byte 1

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