AD8315 datasheet(13/20 Pages) AD

13 / 20 page

REV. B

AD8315

–13–

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata part number

LDC15D190A0007A). This has a coupling factor of approxi-

mately 19 dB for the GSM band and 14 dB for DCS and an

insertion loss of 0.38 dB and 0.45 dB, respectively. Because the

PF08107B transmits a maximum power level of +35 dBm for

GSM and +32 dBm for DCS, additional attenuation of 20 dB is

required before the coupled signal is applied to the AD8315.

This results in peak input levels to the AD8315 of –4 dBm

(GSM) and –2 dBm (DCS). While the AD8315 gives a linear

response for input levels up to +2 dBm, for highly temperature-

stable performance at maximum PA output power, the maxi-

mum input level should be limited to approximately –2 dBm

(see TPC 3 and TPC 5). This does, however, reduce the sensi-

tivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V, is

applied to the VSET Pin of the AD8315. This will typically be

supplied by a digital-to-analog converter (DAC). The AD8315’s

VAPC output drives the level control pin of the power amplifier

directly. VAPC reaches a maximum value of approximately 2.5 V

on a 2.7 V supply while delivering the 3 mA required by the level

control input of the PA. This is more than sufficient to exercise

the gain control range of the PA.

During initialization and completion of the transmit sequence,

VAPC should be held at its minimum level of 250 mV by keeping

VSET below 200 mV.

In this example, VSET is supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC’s output voltage

can be scaled using two resistors as shown. This converts the

DAC’s maximum voltage of 2.55 V down to 1.6 V and increases

the control resolution to 0.25 dB/bit.

A filter capacitor (CFLT) must be used to stabilize the loop. The

choice of CFLT will depend to a large degree on the gain control

dynamics of the power amplifier, something that is frequently

poorly characterized, so some trial and error may be necessary.

In this example, a 150 pF capacitor is used and a 1.5 k

W series

resistor is included. This adds a zero to the control loop and

increases the phase margin, which helps to make the step response

of the circuit more stable when the PA output power is low and

the slope of the PA’s power control function is the steepest.

A smaller filter capacitor can be used by inserting a series

resistor between VAPC and the control input of the PA.

A series resistor will work with the input impedance of the

PA to create a resistor divider and will reduce the loop gain. The

size of the resistor divider ratio depends upon the available

output swing of VAPC and the required control voltage on the PA.

This technique can also be used to limit the control voltage in

situations where the PA cannot deliver the power level being

demanded by VAPC. Overdrive of the control input of some

PAs causes increased distortion. It should be noted, however,

that if the control loop opens (i.e., VAPC goes to its maxi-

mum value in an effort to balance the loop), the quiescent current

of the AD8315 will increase somewhat, particularly at supply

voltages greater than 3 V.

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMM

FLTR

+VS

2.7V

8-BIT

RAMP DAC

0V–2.55V

ENABLE

0V/2.7V

*R2, R3 OPTIONAL,

*SEE TEXT

BAND

SELECT

0V/2V

POUT DCS

32dBm MAX

LDC15D190A0007A

ATTN

20dB

PF08107B

VCTL

VAPC

(OPTIONAL,

SEE TEXT)

PIN GSM

3dBm

PIN DCS

3dBm

ANTENNA

1000pF

3.5V

1000pF

POUT GSM

35dBm MAX

0.1 F

R3*

1.5k

150pF

R2*

600

52.3

49.9

4.7 F

500

AD8315

Figure 8. Dual Mode (GSM/DCS) PA Control Example

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