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PIN FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions—100-Lead EPAD (SV-100)

Pin No.

Mnemonic

I/O

Description

1 to 4, 9 to 12

D7 to D0

I

Parallel Port DATA. Note that the functionality of these pins is valid only when the I/O port is

configured as a parallel port.

5, 6, 21, 28, 95, 96

DGND

Digitial Ground.

7, 8, 20,

23 to 27, 93, 94

DVDD

Digital Supply Voltage.

13 to 18

ADDR5 to

ADDR0

I

When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select

for accessing the on-chip registers (see the IORESET, SDO, and SDIO pins below for serial

port mode).

16

IORESET

I

Note that this is valid only for serial programming mode. Active high input signal that resets the

serial I/O bus controller. It is intended to serve as a means of recovering from an unresponsive

serial bus caused by improper programming protocol. Asserting an I/O reset does not affect the

contents of previously programmed registers nor does it invoke their default values.

17

SDO

O

Note that this is valid only for serial programming mode. When operating the I/O port as a

3-wire serial port, this pin serves as a unidirectional serial data output pin. When operated as a

2-wire serial port, this pin is unused.

18

SDIO

I or

I/O

Note that this is valid only for serial programming mode. When operating the I/O port as a

3-wire serial port, this pin is the serial data input. When operated as a 2-wire serial port, this pin

is the bidirectional serial data pin.

19

WR/SCLK

I

When the I/O port is configured for parallel programming mode, this pin functions as an active

low write pulse (WR). When configured for serial programming mode, this pin functions as the

serial data clock (SCLK).

22

RD/CS

I

When the I/O port is configured for parallel programming mode, this pin functions as an active

low read pulse (RD). When configured for serial programming mode, this pin functions as an

active low chip select (CS) that allows multiple devices to share the serial bus.

29, 30, 37 to 39,

41, 42, 49, 50,

52, 69, 74, 80, 85,

87, 88

AGND

I

Analog Ground.

31, 32, 35, 36,

40, 43, 44, 47,

48, 51, 70, 73,

77, 86, 89, 90

AVDD

I

Analog Supply Voltage.

33

REFCLK

I

Reference Clock Complementary Input. (Note that when the REFCLK port is operated in single-

ended mode, REFCLK should be decoupled to AVDD with a 0.1 µF capacitor.

34

REFCLK

I

Reference Clock Input.

45

LO

I

Mixer Local Oscillator (LO) Complementary Input. Note that when the LO port is operated in

single-ended mode, LO should be decoupled to AVDD with a 0.1 µF capacitor.

46

LO

I

Mixer Local Oscillator (LO) Input.

53

RF

I

Analog Mixer RF Complementary Input. Note that when the RF port is operated in single-ended

mode, RF should be decoupled to AVDD with a 0.1 µF capacitor.

54

RF

I

Analog Mixer RF Input.

55

IF

O

Analog Mixer IF Output.

56

IF

O

Analog Mixer IF Complementary Output.

57

PFD

I

Phase Frequency Detector Complementary Input . Note that when the PFD port is operated in

single-ended mode, PFD should be decoupled to AVDD with a 0.1 µF capacitor.

58

PFD

I

Phase Frequency Detector Input.

59, 60, 75, 76

NC

No Connection.

61

CPISET

I

Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes

the reference current for the charge pump.

62, 67

CPVDD

I

Charge Pump Supply Voltage.

63, 68

CPGND

I

Charge Pump Ground.

64

CPFL

O

Charge Pump Fast Lock Output.

65, 66

CP

O

Charge Pump Output.