AD5696 datasheet(6/24 Pages) AD

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AD5696/AD5694

Data Sheet

Rev. B | Page 6 of 24

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter1, 2

Min

Max

Unit

Description

2.5

µs

SCL cycle time

0.6

µs

tHIGH, SCL high time

1.3

µs

tLOW, SCL low time

0.6

µs

tHD,STA, start/repeated start hold time

100

tSU,DAT, data setup time

t63

0.9

µs

tHD,DAT, data hold time

0.6

µs

tSU,STA, repeated start setup time

0.6

µs

tSU,STO, stop condition setup time

1.3

µs

tBUF, bus free time between a stop condition and a start condition

t104

300

tR, rise time of SCL and SDA when receiving

t114, 5

20 + 0.1CB

300

tF, fall time of SCL and SDA when transmitting/receiving

t12

LDAC pulse width

t13

400

SCL rising edge to LDAC rising edge

tSP6

Pulse width of suppressed spike

CB5

400

Capacitive load for each bus line

See Figure 2.

Guaranteed by design and characterization; not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL

falling edge.

tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

CB is the total capacitance of one bus line in pF.

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

Timing Diagram

Figure 2. 2-Wire Serial Interface Timing Diagram

SCL

SDA

LDAC1

LDAC2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t13

t11

t10

t12

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