AD5724R/AD5734R/AD5754R

Data Sheet

Rev. G | Page 2 of 33

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics................................................ 6

Timing Characteristics ................................................................ 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Architecture................................................................................. 20

Power-Up Sequence ................................................................... 20

Serial Interface ............................................................................ 20

Load DAC (LDAC)..................................................................... 22

Asynchronous Clear (CLR)....................................................... 22

Configuring the AD5724R/AD5734R/AD5754R .................. 22

Transfer Function....................................................................... 22

Input Register.............................................................................. 26

DAC Register .............................................................................. 27

Output Range Select Register ................................................... 27

Control Register ......................................................................... 28

Power Control Register ............................................................. 29

Design Features............................................................................... 30

Analog Output Control ............................................................. 30

Power-Down Mode.................................................................... 30

Overcurrent Protection ............................................................. 30

Thermal Shutdown .................................................................... 30

Internal Reference ...................................................................... 30

Applications Information .............................................................. 31

+5 V/±5 V Operation ................................................................ 31

Alternative Power-Up Sequence Support ............................... 31

Layout Guidelines....................................................................... 31

Galvanically Isolated Interface ................................................. 32

Microprocessor Interfacing....................................................... 32

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 33

REVISION HISTORY

2/2017—Rev. F to Rev. G

Added Power-Up Sequence Section............................................. 20

Changes to Table 8 and Table 9..................................................... 23

Changes to Table 11 and Table 12 ................................................ 24

Changes to Table 14 and Table 15 ................................................ 25

Changes to Analog Output Control Section............................... 30

Added Alternative Power-Up Sequence Support Section,

Figure 49, and Figure 50; Renumbered Sequentially................. 31

2/2016—Rev. E to Rev. F

Changes to Table 2............................................................................ 4

7/2011—Rev. D to Rev. E

5/2011—Rev. C to Rev. D

Changes to Configuring the AD5724R/AD5734R/

AD5754R Section ........................................................................... 22

7/2010—Rev. B to Rev. C

Changes to Table 28........................................................................ 29

5/2010—Rev. A to Rev. B

Changes to Table 5.............................................................................9

Changes to Table 6.......................................................................... 10

3/2009—Rev. 0 to Rev. A

Added AD5724R Model ............................................... Throughout

Added 12-Bit Resolution .............................................. Throughout

Changes to Resolution and Integral Nonlinearity (INL)

Parameters (Table 2)..........................................................................4

Changes to Endnote 2 (Table 2) ......................................................5

Added Endnote 4 (Table 4) ..............................................................6

Added Figure 8 and Figure 11 ...................................................... 11

Added Figure 39 ............................................................................. 16

Added Ideal Output Voltage to Input Code

Relationship—AD5724R Section ................................................. 25

Added Table 21 ............................................................................... 27

Changes to Ordering Guide.......................................................... 32

1/2009—Revision 0: Initial Version