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Data Sheet

AD5025/AD5045/AD5065

Rev. A | Page 17 of 25

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial

input, voltage output DACs. The parts operate from supply voltages

of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065

in a 32-bit word format via a 3-wire serial interface. The AD5025/

AD5045/AD5065 incorporate a power-on reset circuit that ensures

the DAC output powers up to a known output state. The devices

also have a software power-down mode that reduces the typical

current consumption to typically 400 nA.

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by













REFIN

OUT

where:

is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 65,535 for the 16-bit AD5065).

is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5025/AD5045/AD5065 consists

of two matched DAC sections. A simplified circuit diagram is

shown in Figure 40. The four MSBs of the 16-bit data-word are

decoded to drive 15 switches, E1 to E15. Each of these switches

connects one of 15 matched resistors to either GND or a VREF

buffer output. The remaining 12 bits of the data-word drive

Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder

network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 40. DAC Ladder Structure

REFERENCE BUFFER

The AD5025/AD5045/AD5065 operate with an external reference.

Each DAC has a dedicated voltage reference pin and an on-chip

reference buffer. The reference input pin has an input range of

2.5 V to VDD. This input voltage is then used to provide a

buffered reference for the DAC core.

OUTPUT AMPLIFIER

The on-chip output buffer amplifier can generate rail-to-rail

voltages on its output, which gives an output range of 0 V to

VDD. The amplifier is capable of driving a load of 5 k

Ω฀i

parallel with 200 pF to GND. The slew rate is 1.5 V/µs with a ¼

to ¾ scale settling time of 13 µs.

SERIAL INTERFACE

The AD5025/AD5045/AD5065 have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and

MICROWIRE interface standards as well as most DSPs. See

Figure 3 for a timing diagram of a typical write sequence.

INPUT REGISTER

The AD5025/AD5045/AD5065 input register is 32 bits wide

(see Figure 41). The first four bits are don’t cares. The next four

bits are the command bits, C3 to C0 (see Table 8), followed by

the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally

the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit

input code, followed by eight, six, or four don’t care bits for the

AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42,

and Figure 43). These data bits are transferred to the DAC

Table 7. Address Commands

Address (n)

Selected DAC

Channel

DAC A

DAC B

Reserved

Both DACs

Table 8. Command Definitions

Command

Description

Write to Input Register n1

Update DAC Register n1

Write to Input Register n, update all

(software LDAC)

Write to and update DAC Channel n1

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Set up DCEN register (daisy-chain enable)

Reserved

1 See Table 7.

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