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AD5025/AD5045/AD5065

Data Sheet

Rev. A | Page 22 of 25

POWER-DOWN LOCKOUT

The AD5025/AD5045/AD5065 contain a digital input pin, PDL.

When activated, the power-down lockout pin (PDL) disables

software shutdown under any circumstances. The user should

hardwire the PDL pin to a logic low (thus preventing subsequent

software power-down) or logic high (the part can be placed in

power-down mode over the serial interface). If the user transitions

the PDL pin from logic high to a logic low during a valid write

sequence, the device responds immediately and the current

write sequence is aborted. Note the following PDL features.

PDL During a Write Sequence

If a PDL is generated (that is, a high-to-low transition) while a

valid write sequence is ongoing, the write is aborted. The user

must rewrite the current write command again.

PDL While DACs in Power-Down Mode

If a PDL is generated while the DAC(s) are in power-down

mode, the DAC(s) come out of power-down (that is, all power-

down bits are reset to 0000) to the last voltage output correspond-

ing to the last valid stored DAC value. While PDL remains active,

software power-down is disabled.

PDL Low to High Transition

After PDL is taken from a low to a high state, all DAC channels

remain in normal mode, and the user must reissue a software

power-down command to the control register to power down

the required channels.

Transitioning PDL from a low to a high disables the feature

immediately.

If PDL and CLR are generated at the same time, the CLR signal

causes the DAC register to change as per the clear code register,

and the DACs come out of power-down.

If PDL, CLR, and LDAC are generated at the same time, CLR

has higher precedence over LDAC and PDL.

The user is recommended to hardwire the pin to a logic high or

low, thereby either enabling or disabling the feature.

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board (PCB) containing the AD5025/AD5045/

AD5065 should have separate analog and digital sections. If the

AD5025/AD5045/AD5065 are in a system where other devices

require an AGND-to-DGND connection, the connection should

be made at one point only. This ground point should be as close

as possible to the AD5025/AD5045/AD5065.

Bypass the power supply to the AD5025/AD5045/AD5065 with

10 µF and 0.1 µF capacitors. The capacitors should physically be

as close as possible to the device, with the 0.1 µF capacitor

ideally right up against the device. The 10 µF capacitors are the

tantalum bead type. It is important that the 0.1 µF capacitor has

low effective series resistance (ESR) and low effective series

inductance (ESI), which is typical of common ceramic types of

capacitors. This 0.1 µF capacitor provides a low impedance path

to ground for high frequencies caused by transient currents due

to internal logic switching.

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Shield clocks and other fast switching digital signals

from other parts of the board by digital ground. Avoid crossover

of digital and analog signals if possible. When traces cross on

opposite sides of the board, ensure that they run at right angles

to each other to reduce feedthrough effects through the board.

The best board layout technique is the microstrip technique,

where the component side of the board is dedicated to the

ground plane only and the signal traces are placed on the solder

side. However, this is not always possible with a 2-layer board.

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