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AD5444/AD5446

Data Sheet

Rev. F | Page 18 of 28

DAC leakage current is also a potential error source in divider

circuits. The leakage current must be counterbalanced by an

opposite current supplied from the op amp through the DAC.

Because only a fraction (D) of the current into the VREF terminal

is routed to the IOUT1 terminal, the output voltage has to change,

as follows:

Output Error Voltage due to DAC Leakage = (Leakage × R)/D

where R is the DAC resistance at the VREF terminal.

For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain

(1/D) of 16, the error voltage is 1.6 mV.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is

an amplifier with low input bias currents and low input offset

voltage. The input offset voltage of an op amp is multiplied by

the variable gain (due to the code-dependent output resistance

of the DAC) of the circuit. A change in this noise gain between

two adjacent digital fractions produces a step change in the

output voltage due to the amplifier’s input offset voltage. This

output voltage change is superimposed upon the desired change

in output between the two codes and gives rise to a differential

linearity error, which, if large enough, can cause the DAC to be

nonmonotonic.

The input bias current of an op amp also generates an offset

at the voltage output as a result of the bias current flowing

in the feedback resistor, RFB. Most op amps have input bias

currents low enough to prevent any significant errors in

12-bit applications.

Common-mode rejection of the op amp is important in voltage

switching circuits because it produces a code-dependent error

at the voltage output of the circuit. Most op amps have adequate

common-mode rejection for use at 8-bit, 10-bit, and 12-bit

resolutions.

Provided that the DAC switches are driven from true wideband

low impedance sources (VIN and AGND), they settle quickly.

Consequently, the slew rate and settling time of a voltage switching

DAC circuit is determined largely by the output op amp. To

obtain minimum settling time in this configuration, it is impor-

tant to minimize capacitance at the VREF node (voltage output

node in this application) of the DAC. This is done by using low

input, capacitance buffer amplifiers and careful board design.

Most single-supply circuits include ground as part of the analog

signal range, which, in turn, requires an amplifier that can handle

rail-to-rail signals. A large range of single-supply amplifiers is

available from Analog Devices, Inc. (see Table 8 and Table 9 for

suitable suggestions).

REFERENCE SELECTION

When selecting a reference for use with the AD5444/AD5446

current output DAC, pay attention to the output voltage tem-

perature coefficient specification. This parameter affects not

only the full-scale error but can also affect the linearity (INL

and DNL) performance. The reference temperature coefficient

should be consistent with the system accuracy specifications.

For example, an 8-bit system required to hold its overall speci-

fication to within 1 LSB over the temperature range 0°C to 50°C

dictates that the maximum system drift with temperature

should be less than 78 ppm/°C.

A 12-bit system with the same temperature range to overall

specification within 2 LSBs requires a maximum drift of

10 ppm/°C. By choosing a precision reference with low output

temperature coefficient, this error source can be minimized.

Table 7 suggests some of the dc references available from

Analog Devices that are suitable for use with this range of

current output DACs.

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