AD5722R datasheet(22/32 Pages) AD

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AD5722R/AD5732R/AD5752R

Data Sheet

Rev. F | Page 22 of 32

LOAD DAC (LDAC)

After data has been transferred into the input register of the

DACs, there are two ways to update the DAC registers and DAC

outputs. Depending on the status of both SYNC and LDAC, one

of two update modes is selected: individual DAC updating or

simultaneous updating of all DACs.

SYNC

SCLK

VOUTx

DAC

INTERFACE

LOGIC

OUTPUT

AMPLIFIER

LDAC

SDO

SDIN

REFIN

INPUT

12-/14-/16-BIT

DAC

Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the input shift register. The addressed DAC output is updated

on the rising edge of SYNC.

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the input shift register. All DAC outputs are asynchronously

updated by taking LDAC low after SYNC has been taken high.

The update now occurs on the falling edge of LDAC.

ASYNCHRONOUS CLEAR (CLR)

CLR is an active low clear that allows the outputs to be cleared

to either zero-scale code or midscale code. The clear code value

is user selectable via the CLR select bit of the control register

(see the Control Register section). It is necessary to maintain

CLR low for a minimum amount of time to complete the operation

(see Figure 2). When the CLR signal is returned high, the output

remains at the cleared value until a new value is programmed. The

outputs cannot be updated with a new value while the CLR pin

is low. A clear operation can also be performed via the clear

command in the control register.

CONFIGURING THE AD5722R/AD5732R/AD5752R

When the power supplies are applied to the AD5722R/AD5732R/

AD5752R, the power-on reset circuit ensures that all registers

default to 0. This places all channels and the internal reference

in power-down mode. The DVCC must be brought high before

any of the interface lines are powered. If this is not done the first

write to the device may be ignored. The first communication to

the AD5722R/AD5732R/AD5752R should be to set the required

output range on all channels (the default range is the 5 V unipolar

range) by writing to the output range select register. The user

should then write to the power control register to power on the

required channels and the internal reference, if required.

If an external reference source is being used, the internal

reference must remain in power-down mode. To program an

output value on a channel, that channel must first be powered

up; any writes to a channel while it is in power-down mode are

ignored. The AD5722R/AD5732R/AD5752R operate with a

wide power supply range. It is important that the power supply

applied to the devices provides adequate headroom to support

the chosen output ranges.

TRANSFER FUNCTION

Table 8 to Table 16 show the relationships of the ideal input code

to output voltage for the AD5752R, AD5732R, and AD5722R,

respectively, for all output voltage ranges. For unipolar output

ranges, the data coding is straight binary. For bipolar output

ranges, the data coding is user selectable via the BIN/2sCOMP

pin and can be either offset binary or twos complement.

For a unipolar output range, the output voltage expression is

given by









REFIN

OUT

Gain

For a bipolar output range, the output voltage expression is given by

REFIN

OUT

Gain

−









where:

is the decimal equivalent of the code loaded to the DAC.

is the bit resolution of the DAC.

VREFIN

is the reference voltage applied at the REFIN pin.

Gain

is an internal gain whose value depends on the output

range selected by the user, as shown in Table 7.

Table 7.

Output Range (V)

Gain Value

+10

+10.8

4.32

±5

±10

±10.8

8.64

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