M58WR032FT datasheet(32/86 Pages) STMICROELECTRONICS

32 / 86 page

M58WR032FT, M58WR032FB

32/86

other modes, WAIT is always asserted (except for

Read Array mode).

See Table 21., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

Synchronous Burst Read Suspend. A

Syn-

chronous Burst Read operation can be suspend-

ed, freeing the data bus for other higher priority

devices. It can be suspended during the initial ac-

cess latency time (before data is output) in which

case the initial latency time can be reduced to ze-

ro, or after the device has output data. When the

Synchronous Burst Read operation is suspended,

internal array sensing continues and any previous-

ly latched internal data is retained. A burst se-

quence can be suspended and resumed as often

as required as long as the operating conditions of

the device are met.

A Synchronous Burst Read operation is suspend-

ed when E is low and the current address has

been latched (on a Latch Enable rising edge or on

a valid clock edge). The clock signal is then halted

at VIH or at VIL, and G goes high.

When G becomes low again and the clock signal

restarts, the Synchronous Burst Read operation is

resumed exactly where it stopped.

WAIT being gated by E remains active and will not

revert to high-impedance when G goes high. So if

two or more devices are connected to the system’s

READY signal, to prevent bus contention the

WAIT signal of the Flash memory should not be di-

rectly connected to the system’s READY signal.

See Table 21., Synchronous Read AC Character-

istics and Figure 14., Synchronous Burst Read

Suspend AC Waveforms, for details.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

only the first data output after the X latency is valid.

Synchronous Single Reads are used to read the

Electronic Signature, Status Register, CFI, Block

Protection Status, Configuration Register Status

or Protection Register. When the addressed bank

is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is al-

ways asserted.

See Table 21., Synchronous Read AC Character-

istics and Figure 13., Single Synchronous Read

AC Waveforms, for details.

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