tm

May 2007

©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHC573 Rev. 1.3

74VHC573

Octal D-Type Latch with 3-STATE Outputs

Features

General Description

The VHC573 is an advanced high speed CMOS octal

latch with 3-STATE output fabricated with silicon gate

CMOS technology. It achieves the high speed operation

similar to equivalent Bipolar Schottky TTL while main-

taining the CMOS low power dissipation. This 8-bit

D-type latch is controlled by a latch enable input (LE)

and an Output Enable input (OE). When the OE input is

HIGH, the eight outputs are in a high impedance state.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back

up. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Ordering Information

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Description

Order Number

Package

Number

Package Description

74VHC573M

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC573SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC573MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names

Description

Data Inputs

LE

Latch Enable Input

OE

3-STATE Output Enable Input

3-STATE Outputs