uP1536

4

uP1536-DS-P0300, Jul. 2016

www.upi-semi.com

Functional Description

Supply Voltage

The VCC pin receives a well-decoupled 4.5V to 13.2V

supply voltage to power the control circuit, the lower gate

driver and the bootstrap circuit for the higher gate driver.

A minimum 1uF ceramic capacitor is recommended to

bypass the supply voltage. Place the bypassing capacitor

physically near the IC.

The uP1536 integrates MOSFET gate drives that are

powered from the VCC pin and support 12V + 12V and

5V + 19V driving capability.

Power On Reset and Chip Enable

A power on reset (POR) circuitry continuously monitors

the supply voltage at VCC pin. Once the rising POR

the PWM for operation.

The rising POR threshold is typically 4.2V at VCC rising.

The EN pin allows for power sequencing between the

controller bias voltage and another voltage rail. The

uP1536 remains in shutdown if the EN pin is pulled “Lo”.

When EN pin rises above the V

will begin a new initialization and soft-start cycle.

Disable

Enable

GND

EN

FB

Roffset

Rfb

Rb

Cb

Figure 1.

Soft-Start

A built-in soft-start is used to prevent surge current from

power supply input during turn on (referring to the

Functional Block Diagram).

The error amplifier is a three-input device. Reference

voltage (V

whichever is smaller dominates the behavior of the non-

inverting input of the error amplifier.

V

initiated. The ramp is created digitally with numerous small

discrete steps. Each step is with about 10mV incremental.

Accordingly, the output voltage traces the V

ramps up smoothly to its target level. Reference voltage

V

V

uP1536.

Power Input Detection

The uP1536 detects PHASE voltage for the present of

power input when the UGATE trigger minimum pulse in

the beginning. If the PHASE voltage does not exceed 1.5V

during the UGATE on, the uP1536 asserts that power input

is not ready and stops the soft-start cycle. However, the

internal SS continues ramping up to VCC. After that,

another soft-start is initiated. The hiccup period is about

2ms.

Output Voltage Selection

The lower limitation of output voltage is caused by the

internal reference.

The upper limitation of the output voltage is caused by

maximum duty by minimum off time).

This is to leave enough time for over current detection.

Output voltage out of this range is not allowed.

A voltage divider sets the output voltage (refer to the

Typical Application Circuit on page 6 for detail).

In real applications, choose R

Ω

~ 10kΩ range and

choose appropriate Rocset according to the desired output

voltage.

Power OK Indication

The POK is an open-drain output pin to indicate the output

voltage status. It is set high-impedance after soft-start end

and no fault occurs.

Ultrasonic Mode (USM) Operation

The uP1536Q features ultrasonic mode operation that

maintains minimum switching frequency higher than

30kHz and out of audio frequency band. This eliminates

the audio noise that may occur in pulse skipping mode at

very light load condition. In USM, the lower MOSFET turns

on to induce a negative inductor current and discharge

the output capacitor if the switching frequency is lower

than 30kHz. The control loop will initiate an on-time to turn

on upper MOSFET depends on internal COMP. When the

on-time operation expires, the controller re-enables the

lower MOSFET until the inductor current drops below the

zero-crossing threshold.

Over current Protection (OCP)

The uP1536 detects voltage drop across the lower

MOSFET (V

turned on. If V

LGATE are latched “Lo”. It could be reset by POR or

according the on-resistance of the lower MOSFET used.

)

ON

(

DS

OCP

OCP

R

V

I

=

Inductor current ripple should be taken into consideration.

The current near the valley of the ripple current is used

for OCP, resulting the averaged OCP level a little higher

than the calculated value.