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486DX Datasheet(PDF) 1 Page - STMicroelectronics |
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486DX Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 8 page  October 1995 1/8 ST 486 DX ASIC CORE Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE PRELIMINARY DATA s Fully Static 486 compatible core able to operate from D.C to 120MHz s Manufactured in a 0.35 micron five layer metal HCMOS process s 8K byte unified instruction and data cache with write back capability s Parallel processing integral floating point unit, with automatic power down mode s Low Power system management modes s Cell libraries for 2.2V and 3.3V supply with 5 V I/O interface capability s 2 - input NAND delay of 0.160 ns (typ) with fanout = 2. s Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. s High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike sup- pression and impedance matching. s Generators to support SPRAM, DPRAM, ROM and many other embedded functions. s Fully independent power and ground configu- rations for inputs, core and outputs. s Programmable I/O ring capability up to 1000 pads. s Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels. s Active pull up and pull down devices. s Buskeeper I/O functions. s Oscillators for wide frequency spectrum. s Broad range of 400 SSI cells. s Design For Test includes LSSD macro library option and IEEE 1149.1 JTAG Boundary Scan architecture built in. s Cadence based design system with inter- faces from multiple workstations. s Broad ceramic and plastic package range. s Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts. Se a o f G at e s S t a n d ar d C e lls C u s t o m I/ O Pr o g ra m m a b le I/O e .g RAM DAC SV G A CHIP S E T / P C I ID E / IS A 48 6 D X C O R E RO M RAM DP RAM Figure 1. Example 486 DX Core ASIC |
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Similar Description - 486DX |
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