UP7537 datasheet(12/14 Pages) UPI

12 / 14 page

uP7537

uP7537-DS-F0200, Mar. 2013

www.upi-semi.com

Application Information

Thermal Consideration

Temperature effect should be well considered when dealing

with voltage drop and power dissipation. The maximum

DS(ON) of the power switch is 80mΩ of Q1/Q3/Q5 under

25OC junction temperature. If the device is expected to

operate at 125OC junction temperature, the R

DS(ON) of Q1/

Q3/Q5 will become

80m

Ω * (1 + (125OC - 25OC) * 0.5%/OC) = 120mΩ

where 0.5%/OC is the approximated temperature coefficient

of the R

DS(ON).

If the maximum load current is expected to be 1.2A, the

maximum voltage will become

1.2A * 120m

Ω = 144mV

This in turn will cause power dissipation as

1.2A * 144mV = 173mW

The temperature raise is calculated as

173mW * 50OC/W = 8.7OC

The junction temperature is calculated as T

A + 8.7

OC, where

A is the expected maximum ambient temperature. A few

iterations are required until get final solutions.

The thermal resistance

JA highly depends on the PCB

design. Copper plane under the exposed pad is an effective

heatsink and is useful for improving thermal conductivity.

Figure 3 show the relationship between thermal resistance

JA vs. copper area on a standard JEDEC 51-7 (4 layers,

2S2P) thermal test board at T

A = 25

OC. A 50mm2 copper

plane reduces

JA from 75

OC/W to 50OC/W and increases

maximum power dissipation from 1.33W to 2W.

100

Copper Area (mm2)

Figure 3. Thermal Resistance

JA vs. Copper Area

PCB Layout Consideration

Place the uP7537 as close to the USB connector as

possible to minimize the parasitic elements.

Place local bypass capacitors as closed as possible to

the 5VSB and 5VCC pins. Use short and wide traces

to minimize parasitic resistance and inductance.

The exposed pad should be soldered on GND plane

with maximum area and with multiple vias to inner layer

of ground place for improved thermal performance.

Keep the power trace short and wide to minimize the

parasitic resistance along the trace.

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