AD5231 datasheet(6/14 Pages) AD

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PRELIMINARY TECHNICAL DATA

Nonvolatile Memory Digital Potentiometers

AD5231/AD5232/AD5233

REV PrF

22 MAR '01

Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the

information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa

Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com

AD5233 PIN CONFIGURATION

CLK

SDI

SDO

GND

VSS

RDY

VDD

AD5233 PIN FUNCTION DESCRIPTION

Name

Description

Non-Volatile Digital Output #1, ADDR(O1) = 4H, data bit position D0.

CLK

Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges.

SDI

Serial Data Input Pin.

SDO

Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output.

See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock

pulses. This allows daisy-chain operation of multiple packages.

GND

Ground pin, logic ground reference

VSS

Negative Supply. Connect to zero volts for single supply applications.

A terminal of RDAC1.

Wiper terminal of RDAC1, ADDR(RDAC1) = 0H.

B terminal of RDAC1.

A terminal of RDAC2.

Wiper terminal of RDAC2, ADDR(RDAC2) = 1H.

B terminal of RDAC2.

B terminal of RDAC3.

Wiper terminal of RDAC3, ADDR(RDAC3) = 2H.

A terminal of RDAC3.

B terminal of RDAC4.

Wiper terminal of RDAC4, ADDR(RDAC4) = 3H.

A terminal of RDAC4.

VDD

Positive Power Supply Pin. Should be

≥ the input-logic HIGH voltage.

Write Protect Pin. When active low,

WP prevents any changes to the present contents, except retrieving EEMEM content

and RESET.

Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory

default loads midscale 20H until EEMEM loaded with a new value by the user (

PR is activated at the logic high

transition).

Serial Register chip select active low. Serial register operation takes place when

CS returns to logic high.

RDY

Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10.

Non-Volatile Digital Output #2, ADDR(O2) = 4H, data bit position D1.

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