DS3231SN datasheet(15/19 Pages) DALLAS

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Temperature Registers (11h–12h)

Temperature is represented as a 10-bit code with a res-

olution of +0.25°C and is accessible at location 11h

and 12h. The temperature is encoded in two’s comple-

ment format. The upper 8 bits are at location 11h and

the lower 2 bits are in the upper nibble at location 12h.

Upon power reset, the registers are set to a default

temperature of 0°C and the controller starts a tempera-

ture conversion. New temperature readings are stored

in this register.

I2C Serial Data Bus

The DS3231 supports a bidirectional I2C bus and data

transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiv-

ing data is defined as a receiver. The device that con-

trols the message is called a master. The devices that

are controlled by the master are slaves. The bus must

be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions. The DS3231

operates as a slave on the I2C bus. Connections to the

bus are made through the SCL input and open-drain

SDA I/O lines. Within the bus specifications, a standard

mode (100kHz maximum clock rate) and a fast mode

(400kHz maximum clock rate) are defined. The DS3231

works in both modes.

The following bus protocol has been defined (Figure 2):

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain stable

whenever the clock line is high. Changes in the data

line while the clock line is high are interpreted as

control signals.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

high.

Start data transfer: A change in the state of the

data line from high to low, while the clock line is high,

defines a START condition.

Stop data transfer: A change in the state of the data

line from low to high, while the clock line is high,

defines a STOP condition.

Data valid: The state of the data line represents

valid data when, after a START condition, the data

line is stable for the duration of the high period of the

clock signal. The data on the line must be changed

during the low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number

of data bytes transferred between the START and

the STOP conditions is not limited, and is determined

by the master device. The information is transferred

byte-wise and each receiver acknowledges with a

ninth bit.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowledge

after the reception of each byte. The master device

must generate an extra clock pulse, which is associ-

ated with this acknowledge bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the

last byte that has been clocked out of the slave. In

this case, the slave must leave the data line high to

enable the master to generate the STOP condition.

Extremely Accurate I2C-Integrated

RTC/TCXO/Crystal

____________________________________________________________________

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Sign

Data

Temperature Register (Upper Byte) (11h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Data

00000

Temperature Register (Lower Byte) (12h)

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