CY2292
Document #: 38-07449 Rev. *B
Page 5 of 11
Electrical Characteristics, Industrial 5.0V
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = 4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[9]
Except crystal pins
2.0
V
VIL
LOW-Level Input Voltage[9]
Except crystal pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
<1
10
µA
IIL
Input LOW Current
VIN = +0.5V
<1
10
µA
IOZ
Output Leakage Current
Three-state outputs
250
µA
IDD
VDD Supply Current[10] Industrial
VDD = VDD Max., 5V operation
75
110
mA
IDDS
VDD Power Supply Current in
Shutdown Mode[10]
Shutdown active CY2292I/CY2292FI
10
100
µA
Electrical Characteristics, Industrial 3.3V
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOH
HIGH-Level Output Voltage
IOH = 4.0 mA
2.4
V
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-Level Input Voltage[9]
Except crystal pins
2.0
V
VIL
LOW-Level Input Voltage[9]
Except crystal pins
0.8
V
IIH
Input HIGH Current
VIN = VDD – 0.5V
<1
10
µA
IIL
Input LOW Current
VIN = +0.5V
<1
10
µA
IOZ
Output Leakage Current
Three-state outputs
250
µA
IDD
VDD Supply Current[10] Indus-
trial
VDD = VDD Max., 3.3V operation
50
70
mA
IDDS
VDD Power Supply Current in
Shutdown Mode[10]
Shutdown active
CY2292I/CY2292FI
10
100
µA
Switching Characteristics, Commercial 5.0V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range, 5V
operation
CY2292
10
(100 MHz)
13000
(76.923 kHz)
ns
CY2292F
11.1
(90 MHz)
13000
(76.923 kHz)
ns
Output Duty Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHz
40%
50%
60%
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHz
45%
50%
55%
t3
Rise Time
Output clock rise time[13]
35
ns
t4
Fall Time
Output clock fall time[13]
2.5
4
ns
t5
Output Disable Time
Time for output to enter three-state mode
after SHUTDOWN/OE goes LOW
10
15
ns
t6
Output Enable Time
Time for output to leave three-state mode
after SHUTDOWN/OE goes HIGH
10
15
ns
t7
Skew
Skew delay between any identical or
related outputs[3, 12, 14]
< 0.25
0.5
ns
t8
CPUCLK Slew
Frequency transition rate
1.0
20.0
MHz/ms
Notes:
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the
application note: Jitter in PLL-Based Systems.
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