DSP56857 datasheet(351/662 Pages) FREESCALE

351 / 662 page

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-51

12.8.11.1 Prescaler Range (PSR)—Bit 15

This bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends

the range of the prescaler for those cases where a slower bit clock is desired.

•

0 = When the PSR bit is cleared, the fixed prescaler is by-passed.

•

1 = When the PSR bit is set, the fixed divide-by eight prescaler is operational. This allows

a 128kHz master clock to be generated for MC1440x series codecs. The maximum

internally generated bit clock frequency is f IP_CLK /(2×2) and the minimum internally

generated bit clock frequency is f IP_CLK /(4 × 2 × 8 × 256 × 2).

12.8.11.2 Word Length Control (WL)—Bits 14–13

These bits are used to select the length of the data words being transferred by the ESSI. Word

lengths of 8, 10, 12, or 16 bits can be selected. Table 12-17 denotes the WL two-bit field

encoding.

These bits control the Word Length Divider shown in the ESSI Clock Generator. The WL control

bit also controls the frame sync pulse length when the TFSL (or RFSL) bit is cleared.

12.8.11.3 Frame Rate Divider Control (DC)—Bits 12–8

This bit field controls the divide ratio for the programmable frame rate dividers. The divide ratio

operates on the word clock. In the Normal mode, this ratio determines the word transfer rate. The

divide ratio ranges from 1 to 32 (DC[4:0] = 00000 to 11111) in the Normal mode. A divide ratio

of one (DC = 00000) provides continuous periodic data word transfer. A bit-length sync must be

used in this case. In the Network mode, this ratio sets the number of words per frame. The divide

ratio ranges from 2 to 32 (DC[4:0] = 00001 to 11111) in the Network mode. A divide ratio of one

(DC = 00000) in the Network mode is a special case (on Demand mode) not supported.

Table 12-17.

WL Encoding

Number of Bits/Word

DSP56857 Datasheet(PDF) 351 Page - Freescale Semiconductor, Inc