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HT46R65 Datasheet(PDF) 15 Page - Holtek Semiconductor Inc |
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HT46R65 Datasheet(HTML) 15 Page - Holtek Semiconductor Inc |
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15 / 48 page ![]() HT46R65/HT46C65 Rev. 1.80 15 July 14, 2005 Reset There are three ways in which reset may occur. · RES is reset during normal operation · RES is reset during HALT · WDT time-out is reset during normal operation The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the program counter and SP and leaves the other circuits at their original state. Some registers re- main unaffected during any other reset conditions. Most registers are reset to the ²initial condition² once the re- set conditions are met. Examining the PDF and TO flags, the program can distinguish between different ²chip resets². TO PDF RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES Wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT Wake-up HALT Note: ²u² stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys- tem awakes from the HALT state or during power up. Awaking from the HALT state or system power-up, the SST delay is added. An extra SST delay is added during the power-up pe- riod, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status is shown below. Program Counter 000H Interrupt Disabled Prescaler, Divider Cleared WDT, RTC, Time Base Cleared. After master reset, WDT starts counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack R E S V D D 1 0 0 k W 1 0 k W 0 . 1 m F * 0 . 0 1 m F * Reset Circuit Note: ²*² Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. R E S V D D S S T T i m e - o u t C h i p R e s e t t S S T + t O P D Reset Timing Chart W D T H A L T W D T T i m e - o u t R e s e t E x t e r n a l R E S C o l d R e s e t P o w e r - o n D e t e c t i o n S S T 1 0 - b i t R i p p l e C o u n t e r O S C 1 W a r m R e s e t Reset Configuration |
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