42
42
The "Disable Transmitter" command may be
used to cancel any pending transmit command
when the ARCNET core next receives the token.
Normally, in an active network, this command will
set the TA status bit to a logic "1" when the token
is
received.
If
the
"Disable
Transmitter"
command does not cause the TA bit to be set in
the time it takes the token to make a round trip
through the network, one of three situations
exists. Either the node is disconnected from the
network, or there are no other nodes on the
network, or the external receive circuitry has
failed.
These situations can be determined by
either using the improved diagnostic features of
the ARCNET core or using another software
timeout which is greater than the worst case time
for a round trip token pass, which occurs when
all nodes transmit a maximum length message.
Receive Sequence
A receive sequence begins with the RI status bit
becoming a logic "1", which indicates that a
previous
reception
has
concluded.
The
microcontroller
will
be
interrupted
if
the
corresponding bit in the Interrupt Mask Register
is set to logic "1". Otherwise, the microcontroller
must periodically check the Status Register.
Once the microcontroller is alerted to the fact
that the previous reception has concluded, it may
issue
the
"Enable
Receive
to
Page
fnn"
command, which resets the RI bit to logic "0" and
selects a new page in the RAM buffer. Again,
the appropriate buffer size is specified in the
"Define Configuration" command. Typically, the
page which just received the data packet will be
read by the microcontroller at this point.
Once
the
"Enable
Receive
to
Page
fnn"
command is issued, the microcontroller attends
to other duties. There is no way of knowing how
long the new reception will take, since another
node may transmit a packet at any time.
When
another node does transmit a packet to this
node, and if the "Define Configuration" command
has enabled the reception of long packets, the
ARCNET core interprets the packet as either a
long or short packet, depending on whether the
content of the buffer location 2 is zero or non-
zero. The format of the buffer is shown in Figure
12.
Address 0 contains the Source Identifier
(SID),
Address
1
contains
the
Destination
Identifier (DID), and Address 2 contains, for short
packets, the value 256-N, where N represents
the message length, or for long packets, the
value 0, indicating that it is indeed a long packet.
In the latter case, Address 3 contains the value
512-N, where N represents the message length.
Note that on reception, the ARCNET core
deposits packets into the RAM buffer in the same
format that the transmitting node arranges them,
which allows for a message to be received and
then retransmitted without rearranging any bytes
in the RAM buffer other than the SID and DID.
Once the packet is received and stored correctly
in the selected buffer, the ARCNET core sets the
RI bit to logic "1" to signal the microcontroller that
the reception is complete.
COMMAND CHAINING
The
Command
Chaining
operation
allows
consecutive transmissions and receptions to
occur
without
on-chip
80C32
intervention.
Through the use of a dual two-level FIFO,
commands to be transmitted and received, as
well as the status bits, are pipelined.
In order for the COM20051 to be compatible with
previous SMSC ARCNET device drivers, the
device defaults to the non-chaining mode.
In
order to take advantage of the Command
Chaining operation, the Command Chaining
Mode must be enabled via a logic "1" on bit 6 of
the Configuration Register.
In Command Chaining, the Status Register
appears as in Figure 12.
The following is a list of Command Chaining
guidelines for the software programmer. Further
detail can be found in the Transmit Command
Chaining
and
Receive
Command
Chaining
sections.
•
The device is designed such that the
interrupt service routine latency does not
affect performance.
•
Up to two outstanding transmissions and
two outstanding receptions can be pending
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