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DLP2010AFQJ Datasheet(PDF) 4 Page - Texas Instruments |
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DLP2010AFQJ Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 42 page  4 DLP2010 DLPS123 – FEBRUARY 2019 www.ti.com Product Folder Links: DLP2010 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Pin Functions – Connector Pins(1) (continued) PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) NAME NO. (3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET. D_N(3) H1 I SubLVDS Double Data, Negative 7.00 D_P(3) H2 I SubLVDS Double Data, Positive 7.00 DCLK_N H9 I SubLVDS Double Clock, Negative 7.03 DCLK_P H10 I SubLVDS Double Clock, Positive 7.03 CONTROL INPUTS DMD_DEN_ARSTZ G12 I LPSDR(1) Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 5.72 LS_CLK G19 I LPSDR Single Clock for low-speed interface 3.54 LS_WDATA G18 I LPSDR Single Write data for low-speed interface 3.54 LS_RDATA G11 O LPSDR Single Read data for low-speed interface 8.11 POWER VBIAS(3) H17 Power Supply voltage for positive bias level at micromirrors VOFFSET(3) H13 Power Supply voltage for HVCMOS core logic. Includes: supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors VRESET(3) H18 Power Supply voltage for negative reset level at micromirrors VDD(3) G20 Power Supply voltage for micromirror low voltage CMOS core logic includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes. VDD H14 Power VDD H15 Power VDD H16 Power VDD H19 Power VDD H20 Power VDDI(3) G1 Power Supply voltage for SubLVDS receivers VDDI G2 Power VDDI G5 Power VDDI G6 Power VSS(3) G9 Ground Ground. Common return for all power. VSS G10 Ground VSS G13 Ground VSS G14 Ground VSS G15 Ground VSS G16 Ground VSS G17 Ground VSS H3 Ground VSS H4 Ground VSS H7 Ground VSS H8 Ground VSS H11 Ground VSS H12 Ground |
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