FXLP4555MPX datasheet(11/15 Pages) ONSEMI

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FXLP4555 • Rev. 1.0.0

Application Information

Card Supply Converter

The FXLP4555 interface DC-DC converter is a Low

Dropout (LDO) voltage regulator capable of supplying a

current in excess of 50mA under 1.8V or 3.0V.

Quiescent current is typically lower than 20µA (see

Figure 6 and Figure 7).

VSEL is a select input, allowing

a logic level signal to select a regulated voltage of 1.8V

(VSEL = LOW) or 3.0V (VSEL = HIGH).

FXLP4555 has a shutdown input (EN) that allows it to

turn off or turn on the regulator output. Figure 8 shows a

simplified view of the voltage regulator. The VCC_C output

is internally current limited and protected against short

circuits. The short-circuit current (IVCC_C_SC) is constant

over the SIM Card VCC and VBAT, while it varies with

operating temperature, typically in the range of 90mA to

140mA (Figure 4 and Figure 5).

To guarantee a stable LDO, the VCC_C output is

connected to a 1.0µF bypass ceramic capacitor to

ground. At the input, VBAT is bypassed to ground with a

0.1µF ceramic capacitor.

Level Shifters

The level shifters accommodate any voltage difference

between the Baseband (BB) Processor (1.65V – 5.5V)

and the SIM card (1.8V or 3V). The RESET and CLOCK

level shifters are uni-directional (from BB to SIM).

The bidirectional I/O line automatically adapts the

voltage difference between the baseband and the SIM

card in both directions. In addition, with the pull-up

resistor, an active edge rate accelerator circuit (see

Figure

)

provides

fast

charge

the

stray

capacitance, yielding a rise time within the ISO7816-3

specifications.

The typical waveform provided in Figure 10 shows how

the accelerator operates. Two distinct slew rates are

observed. From 0V to approximately VCC/2, the slew

rate is the RC time constant of the pull-up resistor and

the stray capacitance. When the input slope crosses the

VCC/2 threshold, the edge rate accelerator is activated,

resulting in the faster slew rate from approximately

VCC/2 to VCC as depicted in Figure 10.

Figure 8.

Simplified Block Diagram of the LDO

Voltage Regulator

Figure 9.

Basic I/O Line Interface

Figure 10.

SIM_IO Typical Rise and Fall Times with

Stray Capacitance > 30pF

(33pF Capacitor Connected on the Board)

Figure 11. Typical Schmitt Trigger Characteristics

VSEL

VCC_C

VBAT

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