QPL6216Q

High-Linearity SDARS LNA

Data Sheet REV D

Subject to change without notice

4 of 7

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Pin Configuration and Description

Performance Plots

– QPL6216Q-PCB

loss de-embedded.

Pin No.

Label

Description

1

Vbias

Sets the Icq bias point for the device.

2

RF In

RF Input pin. A DC Block is required.

6

Shut Down

A high voltage (>1.17V) turns off the device. If the pin is pulled to ground or driven

with a voltage less than 0.63V, then the device will operate under LNA ON state.

7

RF Out / DCBias

RF Output pin. DC bias will also need to be injected through a RF bias

choke/inductor for operation.

3, 4, 5, 8

NC

No electrical connection. Provide grounded land pads for PCB mounting integrity.

Backside Paddle

RF/DC GND

RF/DC ground. Use recommended via pattern to minimize inductance and

thermal resistance; see PCB Mounting Pattern for suggested footprint.