Everest Semiconductor

ES7148

Rev 6.0

September 2018

Latest datasheet: http://www.everest-semi.com or info@everest-semi.com

2

1. PIN DESCRIPTIONS

PIN

PIN

I/O

DESCRIPTION

1

SCLK

I

Bit clock input

2

LRCK

I

Left and right channel clock input indicating input data sampling

rate (Fs) and channel selection

3

CLKIN

I

System clock input

4

CAP1

O

Filtering capacitor

5

CAP2

O

Filtering capacitor

6

AOUTLN

O

Analog output of left channel

7

NC

I

No connect

8

GND

I

Ground

9

VDD

I

Device power supply

10

AOUTRN

O

Analog output of right channel

11

NC

I

No connect

12

SDATA

I

Serial audio data input

2. RECOMMENDED APPLICATION CIRCUIT

SCLK

1

LRCK

2

AOUTLN

6

AOUTRN

10

SDATA

12

NC

11

CLKIN

3

NC

7

PGND

13

ES7148

AGND

CPU/DSP

3.3uF

3.3uF

470R

470R

2200pF

2200pF

AOUTRN

AOUTLN

AGND

AGND

For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible

Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help

*

1uF

1uF

AGND

AGND

*

*

AGND

0R

GND(SYS)

In the layout, chip is treated as an analog device

AGND

1uF

AGND

VDD

*

Figure 1 Recommended Application Circuit

ES7148

VDD

GND

NC

9

8

7

SCLK

LRCK

CLKIN

1

2

3