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FM8PC71AMAEP Datasheet(PDF) 48 Page - Feeling Technology Corp. |
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FM8PC71AMAEP Datasheet(HTML) 48 Page - Feeling Technology Corp. |
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48 / 73 page ![]() FM8PC71AM This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. P.48 R1.1.004, Aug 7, 2017 FM8PC71AM 遠翔科技 Feeling Technology Address 25H: PWM3Timer Low byte value Register (P3TMLB) Bits 7 6 5 4 3 2 1 0 Name P3TM[7:0]/ Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Name N3[7:0] Default 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit[7:0] : P3TM[7:0] PWM3 Timer Low byte read only Bit[7:0] :N3[7:0] Divider parameter by (N3+1) for Fcpu/Firc/fosc write only, read by IOSTR. Address 25H: PWM3 Timer Divider parameter Register (N3) Bits 7 6 5 4 3 2 1 0 Name N3[7:0] Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Read only by IOSTR instruction Bit[7:0] : N3[7:0] Divider parameter by (N3+1) for Fcpu/Firc/fosc Read only Address 26H: PWM3 Timer compared or overflow reload Low byte value Register (P3RDLB) Bits 7 6 5 4 3 2 1 0 Name P3TRD [7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit[7:0] : P3TRD [7:0] PWM3 Timer compared or overflow reload Low byte Address 27H: PWM3 Timer and reload High-nibble bits Register(P3TRHB) Bits 7 6 5 4 3 2 1 0 Name P3TM [11:8] P3TRD [11:8] Read/Write R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit[7:4] : P3TM[11:8] PWM3 Timer high-nibble bits Bit[3:0] : P3TRD [11:8] PWM3 Timer compared or overflow reload high-nibble bits. |
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