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CLC503 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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CLC503 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 6 page ![]() PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES Ambient Temperature CLC503 +25˚C +25˚C -40 to 85˚C FREQUENCY DOMAIN RESPONSE Differential Amp large signal bandwidth Vo < 4.0Vpp 180 80 70 MHz gain flatness DC to 10MHz 0.3 0.5 0.5 dB Common-Mode Amp -3dB bandwidth Vo < 4.0Vpp 15 10 10 MHz TIME DOMAIN RESPONSE Differential Amp rise and fall time 2V step 2.1 2.5 3.0 ns settling time to 0.1% 2V step 15 22 25 ns overshoot 2V step 0 % slew rate 2V step 800 500 500 V/ µs Common-Mode Amp recovery from power down 0.1% output settling 40 100 100 ns DISTORTION AND NOISE RESPONSE 2nd harmonic distortion 4Vpp, 1MHz -78 -74 -70 dBc B 4Vpp, 10MHz -75 -71 -71 dBc B 3rd harmonic distortion 4Vpp, 1MHz -85 -80 -79 dBc B 4Vpp, 10MHz -77 -72 -72 dBc B SNR 4Vpp 72 71 70 dB integrated output noise voltage Rs = 50Ω 10kHz – 500MHz 325 380 460 µV rms STATIC DC PERFORMANCE Differential Amp gain Vo(Diff)/Vin 2 1.75 - 2.25 1.75 - 2.25 V/V A output offset voltage Vin = 0 10 90 100 mV A INL 0.015 0.03 0.05 % A Rin 2 1.6 - 2.4 1.6 - 2.4 k Ω Common-Mode Amp gain Vocm/Vcm 0.97 0.9 - 1.1 0.9 - 1.1 V/V output offset voltage 100 200 200 mV A Rin 10 5 5 M Ω input voltage range 1.5 - 3.5 V power supply rejection ratio DC 50 30 30 dB A supply current RL= ∞ 25 30 30 mA A supply current, power down 4.5 6 6 mA A MISCELLANEOUS PERFORMANCE power down input CMOS levels 0.5 - 4.8 V C VIL on 1 V VIH off 4.5 V C power down dissipation PDN = “Hi” 45 60 60 mW A output voltage range single output 0.7 - 3.9 0.85 - 3.7 0.9 - 3.5 V differential output resistance 500 400 - 600 375 - 625 Ω Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Electrical Characteristics (V CC = + 5V, VEE = - 5V, Vcm = 2.25V, CL = 5pF, Vo = 4Vpp unless specified) Notes A) J-level: spec is 100% tested at +25˚C, sample tested at +85˚C. LC/MC-level: spec is 100% wafer probed at +25˚C. B) J-level: spec is sample tested at +25˚C. C) POWER DOWN must be 1V higher than Vcm. Ordering Information Model Temperature Range Description CLC503AJE -40˚C to +85˚C 8-pin SOIC Absolute Maximum Ratings supply voltage ±6V maximum input range ±6V maximum output range (±V) 0 to VCC maximum operating temperature range -40˚C to +85˚C maximum junction temperature +175˚C maximum storage temperature range -65˚C to +150˚C maximum lead temperature (soldering 10 sec) +300˚C ESD rating (human body model) 500V Recommended Operating Conditions supply voltage ±4.5 to ±5.5Vdc input voltage ±1V output voltage +0.8 to +3.75V ambient temperature range -40°C to +85°C Package Thermal Resistance Package q JC q JA SOIC (AJE) 65˚C/W 90˚C/W http://www.national.com 2 |
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