MSM6996 datasheet(13/21 Pages) OKI

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¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

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TIMING DIAGRAM

Wave Time Measurement Level

tWX

tIr

tIf

tDOf

2.4 V

1.4 V

0.4 V

Note: Timing between signal waves is judged at 1.4 V

2.4 V

1.4 V

0.4 V

tWR

Basic Timing

XCLOCK

tXS

tXD1

tXD2

tXD3

tSX

1/fC

tWX

tSD

MSD

tRS tSR

tWR

tDS tDH

Transmitter

Section

Receiver

Section

XSYNC

PCMOUT

RCLOCK

RSYNC

Note 1):

When tXS £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tXD1.

When tSX £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tSD.

Note 2):

Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be

asynchronous mutually.

Note 3):

The threshold level is 1.4 V.

tDS tDH

PCMIN

MSD

Invalid Data

Figure 1

Figure 2

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