¡ Semiconductor

MSM7533H/7533V/7534

7/18

DOUT1

PCM signal output of channel 1 when the parallel mode is selected.

The PCM output signal is output from MSD in a sequential order, synchronizing with the rising

edge of the BCLK signal.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK

and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance sate during power saving or power down mode.

When the serial mode is selected, this pin is for the output of serial multiplexed 2ch PCM signal.

A pull-up resistor must be connected to this pin because it is an open drain output.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The MSM7534(A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7533H (

m-law)

MSD

1000

0000

1111

1111

0111

1111

0000

0000

MSM7534 (A-law)

MSD

1010

1010

1101

0101

0101

0101

0010

1010

DOUT2

PCM signal outputs for channel 2 when the parallel mode is selected.

The PCM output signal is output from MSD in a sequential order, synchronizing with the rising

edge of the BCLK signal.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK

and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance state during power saving or power down modes.

When the serial mode is selected, this pin is left open.

A pull-up resistor must be connected to this pin because it is an open drain output.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The MSM7534(A-law) outputs the character signal, inverting the even bits.