¡ Semiconductor

MSM7543/7544

7/19

DG

Ground for the digital signal circuits.

This ground is separate from the analog signal ground. The DG pin must be connected to the AG

pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.

A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.

The PCM output signal is output from MSD in a sequential order, synchronizing with the rising

edge of the BCLOCK signal.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between

BCLOCK and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance state during power saving or power down modes.

A pull-up resistor must be connected to this pin because its output is configured as an open drain.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The MSM7544(A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7543 (

m-law)

MSD

1000

0000

1111

1111

0111

1111

0000

0000

MSM7544 (A-law)

MSD

1010

1010

1101

0101

0101

0101

0010

1010

SG

Signal ground voltage output.

The output voltage is 1/2 of the power supply voltage.

The output drive current capability is

±300 mA.

This pin provides the SG level for CODEC peripherals.

This output voltage level is undefined during power saving or power down modes.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.

Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and

the SGC pin.