EM5106VT datasheet(9/10 Pages) EXCELLIANCE

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2013/11/26

A.3

EM5106

Functional Description

Enable Function

EM5106 is enabled if the voltage of the EN pin is

greater than 1.1V. If the voltage of the EN pin is

less than 0.3V, the IC will be disabled. The

quiescent current can be decreased to be less than

10uA typically.

POR – Power ON Reset

To let EM5106 start to operation, CNTL voltage

must be higher than its POR voltage even when EN

voltage is pulled higher than enable high voltage.

Typical POR voltage is 2.7V.

VOUT Voltage Adjustment

The VOUT voltage of EM5106 can be adjusted by

external

voltage

divider.

Refer

typical

application circuit, VOUT voltage is calculated by

the following equation,

VOUT = (1 + R1/R2) x 0.8V

Over Current Limit Function

EM5106 features over current limiting function

which can limit its output current to 4.5A. When

current limit lasts over one millisecond, IC turns-off

the power device for few milliseconds and then

re-starts.

Input and Output Capacitor Selection

For CNTL pin, a 1uF ceramic capacitor is enough for

bypass the supply of CNTL to GND. For VIN pin,

10uF or larger ceramic capacitor is required to

provide bypass path in transient current demand.

VOUT pin is also recommended to have 10uF or

larger ceramic capacitor to be stable and reduce

the VOUT voltage dip when fast loading transient is

happened. A feed-forward capacitor can be placed

between VOUT and FB pin to speed up the

transient response, optionally.

Power Dissipation

The max power depends on some conditions,

including of thermal impedance, PCB layout,

airflow, and so on. The max power dissipation can

be calculated by the formula as below

PD(max)=(TJ(max)-TA) / θJA

TJ(max) is the max junction temperature; θJA is the

thermal impedance from junction to ambient. The

thermal impedance θJA of DFN3x3-10L is package

design and PCB design dependent. The thermal

impedance can be reduced by increasing the

copper area under the exposed pad of the

DFN3x3-10L package. So, to let the copper area as

large as possible is helpful for the thermal

performance of the DFN3x3-10L package.

For recommended specification of EM5106, the

max junction temperature is 125 degree C. The θJA

of DFN3x3-10L is 60°C/W on the standard JEDEC

51-7(4 layers, 2S2P, copper 2 oz) thermal test

board. The max power dissipation (at 25°C ambient,

on the min exposed pad layout) can be calculated

as below:

PD(max at 25°C)=(125°C–25°C)/(60°C/W) = 1.67W

EM5106VT Datasheet(PDF) 9 Page - Excelliance MOS Corp.

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