¡ Semiconductor

MSM7716

7/22

PCMOUT

PCM signal output.

The PCM output signal is output from MSD in sequential order, synchronously with the rising

edge of the BCLK signal.

MSD may be output at the rising edge of the SYNC signal, depending on the timing between

BCLK and SYNC.

This pin is in high impedance state except during 14-bit PCM output. It is also high impedance

during power saving or power down mode.

A pull-up resistor must be connected to this pin, because its output is configured as an open

drain.

The output coding format is in 14-bit 2's complement.

The MSD represents a polarity of the signal with respect to the signal ground.

Table 1

Input/Output Level

+Full scale

+1

0

–Full scale

PCMIN/PCMOUT

MSD

0111

1111

1111

11

0000

0000

0000

01

0000

0000

0000

00

1000

0000

0000

00

–1

1111

1111

1111

11

PDN

Power down control signal input.

A digital "L" level drives both transmit and receive circuits to a power down state.

The control registers are set to the initial state.

SGC

Connection of a bypass capacitor for generating the signal ground voltage level.

Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and

the SGC pin.