AT84CS001VTP datasheet(3/8 Pages) ATMEL

3 / 8 page

AT84CS001

5402AS–BDC–11/04

Figure 1. Device Pinout

Table 1. Description of Main Functions

Name

Function

Name

Function

VCCD

Digital 3.3V power supply

D0…D9

In-phase output data port D

PLUSD

Output 2.5V power supply

D0N…D9N

Inverted phase output data port D

GND

Ground

DOR/DRDN

DORN/DRD

Additional output bit port D or port D

output clock in staggered mode

CLK, CLKN

Input clock signals

DAO, DAON

Output signals for stand-alone delay cell

I0…I9

In-phase input data (true)

DAI, DAIN

Input signals for stand-alone delay cell

I0N…I9N

Inverted phase input data (false)

DACTRL

Control signal for standalone delay cell

IOR, IORN

Additional input bit

CLKDACTRL

Control signal for clock delay cell

DR/DRN

Output clock signals

DAEN

Enable signal for standalone delay cell

A0…A9

In-phase output data port A

ASYNCRST

Asynchronous reset signal

A0N…A9N

Inverted phase output data port A

SLEEP

Sleep mode selection signal

AOR/DRAN

AORN/DRA

Additional output bit port A or port A

output clock in staggered mode

DMUX ratio selection signal

B0…B9

In-phase output data port B

CLKTYPE

Input clock type selection signal

B0N…B9N

Inverted phase output data port B

DRTYPE

Output clock type selection signal

BOR/DRBN

BORN/DRB

Additional output bit port B or port B

output clock in staggered mode

STAGG

Staggered mode selection for data

outputs

C0…C9

In-phase output data port C

BIST

Built-in self test enable

C0N…C9N

Inverted phase output data port C

DIODE

Diode for die junction temperature

monitoring

COR/DRCN

CORN/DRC

Additional output bit port C or port C

output clock in staggered mode

AT84CS001

[I0…I9]

[I0N…I9N]

CLK, CLKN

ASYNCRST

CLKDACTRL

SLEEP

STAGG

CLKTYPE

DAEN

BIST

DRTYPE

DAI, DAIN

[A0…A9]

[A0N…A9N]

[B0…B9]

[B0N…B9N]

[C0…C9]

[C0N…C9N]

[D0…D9]

[D0N…D9N]

BOR, DRBN

BORN/DRB

AOR, DRAN

AORN/DRA

COR, DRCN

CORN/DRC

DOR, DRDN

DORN/DRD

DAO, DAON

DIODE

GND

VCCD

VPLUSD

DACTRL

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